So far we have assumed that high and low voltages correspond to logic 1 and 0, or TRUE and FALSE, known as active high or positive logic. We can make the opposite statement: low voltage for logic 1 and high voltage for logic 0. The use of negative logic is sometimes preferred over positive logic for applications where it is more restrictive than enable.
Figure 2.19 shows an illustration of AND-OR and NAND-NOR gate pairs for positive and negative logic. The positive logic of an AND gate behaves like the negative logic of an OR gate. Logic gates are physically the same regardless of whether they are positive or negative, only the interpretation of the signals changes.
Figure 2.19: Positive and negative logic for AND-OR and NAND-NOR pairs.
Mixing positive and negative logic in a system is best avoided to prevent confusion, but sometimes it is unavoidable. In these cases, a technique known as "bubble matching" helps to keep the logic running correctly. The idea is that the positive logic circuit is positive and is fitted with a "bubble" (meaning inversion) for all inputs and outputs to be connected to the negative logic circuit. Thus the signal coming out of the bubble is the complement of the signal going into it.
Consider the circuit shown in Figure 2.20a, 2 positive logic circuits are combined with AND gates and connected into a positive logic system. The logically equivalent system is shown in Figure 2.20b. In the bubble matching process, bubbles are attached to each input or output of the active low circuit as in Figure 2.20c.
To facilitate the circuit analysis, the active low input bubbles need to be matched with the active low output bubbles. In Figure 2.20c there are unmatched bubbles because there is only 1 bubble in 1 line. DeMorgan's theorem is used for the conversion from an OR gate to a NAND gate with complemented inputs. Figure 2.20d shows the matched bubbles.
Figure 2.20: Bubble matching process
Sum of Product Form & Logic Diagram
For example, we will create a more complex function than just a simple logic gate, such as the majority function shown as a truth table in Figure 2.16. The majority function will be true if more than half of the inputs are true. This function is often used in error correction by assuming that the value that appears most often is the result value, or sometimes also called a voting function.
Since the discussion up to here does not have a simple gate that can be used directly to implement the majority function, then we will do a transformation of the two-level AND-OR equation and implement it in the form of logic gates from the set {AND, OR, NOT} (for example). It is called a two-level equation because there is one level of AND form followed by one level of OR form. The Boolean function for this majority is true if the value of F in the truth table is true. Thus F will be true for the values A = 0, B = 1, and C = 1, or A = 1, B = 0, and C = 1, and so on as in the table.
Figure 2.16: Truth table for the majority function
One way to write a logical equation is to use the sum-of-product or SOP form, which is a collection of ANDs of the variables involved and then operated with OR. The logical equation form for the majority function is written in Equation 2.1. The '+' sign means the OR operation and not arithmetic addition.
By observing the equation we can determine that 4 AND gates are needed to implement the multiplication term. 
The output of the AND gate is then connected to the input of a 4-input OR gate as shown in Figure 2.17. This circuit demonstrates the majority function, and we can check it by inputting all possible combinations of inputs and observing the results.
If each term contains exactly 1 of each variable, in complement form or not, then this term is called a minterm. The minterm has a value of 1 in the truth table output. Thus the minterm is the minimum term that produces true. Alternatively the function can be written as the sum of the true combinations. Equation 2.1 can be rewritten as equation 2.2 with the index is the minterm index as in Figure 2.16.
This notation is used formally as a Boolean equation because it contains only minterms. Equations 2.1 and 2.2 are referred to as the formal notation for the SOP form.
Figure 2.17: Implementation of the majority function with two-level AND-OR. The inverter does not count as a level.
Product of Sum Form
As a counterpart to the sum-of-product form, Boolean equations can be represented in the product-of-sum (POS) form. An equation in the POS form is a collection of OR circuits whose outputs are connected together with AND gates. One way to form a POS is by complementing the SOP form, and then applying DeMorgan's theorem. For example, look again at the majority function in truth table form in Figure 2.16, the complement form of which is the rows that produce output 0, as in equation 2.3:
Complementing both sides yields equation 2.4:
The application of DeMorgan's theorem in the form of 
equation 2.5 is obtained:
The application of DeMorgan's theorem in the form of 
factors in brackets yields equation 2.6.
Figure 2.18: Two-level OR-AND circuit implementation of the majority function. The inverter does not count as a level.
Equation 2.6 is in POS form, and contains 4 maxterms, allowing each variable to appear exactly once in complemented or uncomplemented form. A maxterm, for example (A + B + C), has the value 0 for one row in the truth table. An equation containing only maxterms in POS form is said to be a product-of-sum equation. An OR-AND circuit as an implementation of equation 2.5 is shown in Figure 2.18.
One motivation for using POS instead of SOP is if it results in a simpler form of the Boolean equation. A simpler Boolean equation may result in a simpler circuit, but this is not certain because there are a number of factors that are not directly dependent on the size of the Boolean equation, such as the complexity of the wiring topology.
Gate count is a measure of circuit complexity that indicates the number of all logic gates used. Gate input count is another measure of circuit complexity that indicates the number of inputs to all logic gates. For the circuits in Figures 2.17 and 2.18, the gate count is 8 and the gate input count is 19 for both the SOP and POS forms. In this case there is no difference in circuit complexity between the SOP and POS forms, but in other cases the difference becomes apparent. There are many different methods for reducing the complexity of digital circuits, some of which are discussed in Chapter 4.