The microcontroller control program is composed of a collection of instructions, these instructions are equivalent to human language command sentences that only consist of predicates and objects. Thus the first stage of creating a microcontroller control program begins with the introduction and understanding of what predicates (verbs) and objects the microcontroller has.
Getting to Know the Microcontroller Instruction Set
Objects in microcontroller programming are data stored in memory, registers and input/output. While the commonly known 'verbs' are grouped into commands for data transfer, arithmetic, logical operations, program flow settings and some special things. The combination of 'verbs' and objects is what forms the microcontroller work control commands.
The MOV A,$7F instruction is an example of a very specific basic instruction, MOV is a 'verb' that commands data copying, is the predicate in this command sentence. While the object is the data that is copied, in this case the data in memory number $7F is copied to Accumulator A.
1. Data mention in MCS51
Data can be in various different places, so there are several ways to address data (often referred to in English as 'Addressing Mode'), including the following.
1. Constant data addressing mode (immediate addressing mode)
MOV A,#$20. Constant data is data that is in the instruction. This example instruction has the meaning of constant data $20 (as constant data is marked with '#') copied to Accumulator A. What really needs to be noted in this command is that the number $20 is part of the instruction.
2. Direct data addressing mode
This method is used to refer to data in memory by mentioning the memory number where the data is located: MOV A,$30. This instruction example has the meaning that the data in memory number $30 is copied to the Accumulator. At first glance, this instruction is the same as the constant data instruction above, the difference is that the instruction above uses the '#' sign which marks $20 as constant data, while in this instruction because there is no '#' sign, $30 is the number of memory.
3. Indirect addressing mode
This method is used to refer to data in memory, if the location of the memory storing the data changes so that the memory number is not called directly but is 'assigned' to another register: MOV A,@R0.
4. In this instruction, the general-purpose register R0 is used to record the memory number, so this instruction has the meaning that the memory whose number is recorded in R0 has its contents copied to Accumulator A.
5. The '@' sign is used to mark the memory number stored in R0.
6. Compare this with the instruction to directly mention the memory number above, in this instruction the memory number is first stored in R0 and R0 plays a role in indicating which memory is used, so if the value of R0 changes the memory indicated will also change.
7. In this instruction, the general-purpose register R0 functions as an address storage register (indirect address register), besides R0, the general-purpose register R1 can also be used as an address storage register.
8. Addressing data in register (register addressing mode)
MOV A,R5. This instruction means that the data in the general-purpose register R5 is copied to Accumulator A. This instruction makes the general-purpose registers R0 to R7 a very practical data storage place that works very quickly.
9. The data referred to in the discussion above are all in data memory (including general-purpose registers which are also located in data memory). In writing programs, it is often necessary to have a standard table that is stored together with the program. This kind of table is actually data that is in program memory!
10. For this purpose, MCS51 has a way of addressing data in program memory which is done indirectly (code indirect addressing mode): MOVC A,@A+DPTR.
Note that in this instruction MOV is replaced with MOVC, the additional letter C is intended to distinguish that this instruction is used in program memory. (MOV without the letter C means the instruction is used in data memory).
The '@' sign is used to mark A+DPTR used to indicate the memory number whose contents are copied to Accumulator A, in this case the value stored in DPTR (Data Pointer Register - 2 bytes) plus the value stored in Accumulator A (1 byte) is used to indicate the program memory number.
Overall, the AT8951 has 255 kinds of instructions, which are formed by combining 'verbs' and objects. These 'verbs' are discussed as a group as follows:
2. Copy data instructions
The basic code for this group is MOV, short for MOVE which means to move, although it is more appropriate to say that this command has the meaning of copying data. This can be explained as follows: after the MOV A,R7 instruction is executed, Accumulator A and general-purpose register R7 contain the same data, which was originally stored in R7.
The MOV command is distinguished according to the type of AT89Cx051 memory. This command in data memory is written as MOV, for example:
MOV A,$20
MOV A,@R1
MOV A,P1
MOV P3,AFor use in program memory, this command is written as MOVC, there are only 2 types of instructions that use MOVC, namely:
MOVC A,@A+DPTR ;DPTR sebagai register indirect
MOVC A,@A+PC ;PC sebagai register indirectIn addition, the MOVX command is also known, namely the command used for external data memory (X stands for External). This command is only owned by members of the MCS51 family that have external data memory, for example AT89C51 and so on, and is clearly not known by the AT89Cx051 group that does not have external data memory. There are only 6 types of instructions that use MOVX, these instructions are:
MOVX A,@DPTR
MOVX A,@R0
MOVX A,@R1
MOVX @DPTR,A
MOVX @R0,A
MOVX @R1,A| Mnemonic | Operation | Addressing Mode | | | | Exect. |
|-------------------|----------------------------------|-------------------|-----|-----|-----|----------|
| | | Dir | Ind | Reg | Imm | Timer uS |
| Mov A,<src> | A=<src> | V | V | V | V | 1 |
| Mov <dest>,A | <dest>=A | V | V | V | V | 1 |
| Mov <dest>, <src> | <dest>=<src> | V | V | V | V | 1 |
| Mov DPTR,#data16 | DPTR=16 bit immediate const | Accumulator Only | | | | 1 |
| Push <src> | Inc SP | V | V | V | | 1 |
| Pop <src> | Dec SP | Data Pointer Only | | | | 2 |
| Xch A,<byte> | Acc and <byte> exchange data | Accumulator Only | | | | 1 |
| Xchd A,@Ri | Acc and @Ri exchange low nibbles | V | V | V | | 1 |3. Arithmetic Instructions
ADD and ADDC commands
The contents of Accumulator A are added with a 1 byte number, the result of the addition will be stored back in the Accumulator. In this operation, the Carry bit (C flag in PSW -- Program Status Word) functions as a container for overflowing the addition result. If the addition result is overflowing (its value is greater than 255) the Carry bit will be worth '1', otherwise the Carry bit will be worth '0'. ADDC is the same as ADD, except that in ADDC the Carry bit value in the previous process is also added together.
The 1 byte number added to the Accumulator can come from a constant number, from a general-purpose register, from data memory whose memory number is mentioned directly or indirectly, as seen in the following example:
ADD A,R0 ; register serba guna
ADD A,#$23 ; bilangan konstan
ADD A,@R0 ; no memori tak langsung
ADD A,P1 ; no memori langsung (port 1)SUBB command
The contents of Accumulator A are reduced by the following 1 byte number with the Carry bit value, the result of the subtraction will be stored back in the Accumulator. In this operation the Carry bit also functions as a container for overflowing the subtraction result. If the subtraction result is overflowing (its value is less than 0) the Carry bit will have a value of '1', otherwise the Carry bit has a value of '0'.
SUBB A,R0 ; A = A - R0 - C
SUBB A,#$23 ; A = A - $23
SUBB A,@R1
SUBB A,P0DA Command
The DA (Decimal Adjust) command is used after the ADD; ADDC or SUBB command, used to change the 8-bit binary value stored in the Accumulator into 2 decimal numbers, each consisting of a 4-bit binary value.
MUL AB command
The 8-bit binary number in Accumulator A is multiplied by the 8-bit binary number in register B. The result of the multiplication is a 16-bit binary number, the 8 bits of the binary number with the larger weight are stored in register B, while the other 8 bits with the smaller weight are stored in Accumulator A.
The OV bit in the PSW (Program Status Word) is used to mark the multiplication result value in register B. The OV bit will be '0' if register B is worth $00, otherwise the OV bit is '1'.
MOV A,#10
MOV B,#20
MUL ABDIV AB Command
The 8-bit binary number in Accumulator A is divided by the 8-bit binary number in register B. The result of the division in the form of an 8-bit binary number is stored in the Accumulator, while the remainder of the division in the form of an 8-bit binary number is stored in register B.
The OV bit in the PSW (Program Status Word) is used to mark the value before division in the B register. The OV bit will be '1' if the original B register is $00.
Table 1.3. Arithmetic Instructions
| Mnemonic | Operation | Addressing Mode | | | | Exect. |
|---------------|-----------------------|------------------------|-----|-----|-----|----------|
| | | Dir | Ind | Reg | Imm | Timer uS |
| Add A,<byte> | A=A+<byte> | V | V | V | V | 1 |
| Addc A,<byte> | A=A+<byte>+C | V | V | V | V | 1 |
| Subb A,<byte> | A=A-<byte>-C | V | V | V | V | 1 |
| Inc A | A=A+1 | Accumulator Only | | | | 1 |
| Inc <byte> | <byt>=<byt>+1 | V | V | V | | 1 |
| Inc DPTR | DPTR=DPTR+1 | Data Pointer Only | | | | 2 |
| Dec A | A=A-1 | Accumulator Only | | | | 1 |
| Dec <byte> | <byt>=<byt>-1 | V | V | V | | 1 |
| Mul AB | B:A=BxA | Accumulator and B Only | | | | 4 |
| Div AB | A=Int[A/B] B=Mod[A/B] | Accumulator and B only | | | | 4 |
| DA A | Dec Adjust | Accumulator Only | | | | 1 |4. Logic Instructions
This group of commands is used to perform logical operations on the MCS51 microcontroller, the logical operations that can be performed are AND operations (ANL operation code), OR operations (ORL operation code) and Exclusive-OR operations (XRL operation code).
The data used in this operation can be data in the Accumulator or data in data memory, this is slightly different from arithmetic operations that must display the Accumulator actively. The results of the operation are stored in the first data source.
AND logic operation is widely used to '0' certain bits of an 8-bit binary number, by forming an 8-bit binary number as constant data that is ANL-ed the original number. The bit to be '0' is represented by '0' in the constant data, while the other bits are given the value '1', for example. The ANL instruction P1,#%01111110 will cause bits 0 and 7 of Port 1 (P1) to have the value '0' while the other bits remain unchanged.
The OR logic operation is widely used to '1' certain bits of an 8-bit binary number, by forming an 8-bit binary number as constant data that is ORLed to the original number. The bit to be '1' is represented by '1' in the constant data, while the other bits are given the value '0', for example: The ORL instruction A,#%01111110 will cause bits 1 to 6 of the Accumulator to have a value of '1' while the other bits remain unchanged.
Exclusive-OR logic operation is widely used to reverse the value (complement) of certain bits of an 8-bit binary number, by forming an 8-bit binary number as constant data that is XRL-ed the original number. The bit to be reversed is represented by '1' in the constant data, while the other bits are given the value '0', for example: The XRL A,#%01111110 instruction will cause bits 1 to 6 of the Accumulator to reverse value, while the other bits remain unchanged.
| Mnemonic | Operation | Addressing Mode | | | | Exect. |
|------------------|-----------------------------|------------------------|-----|-----|-----|----------|
| | | Dir | Ind | Reg | Imm | Timer uS |
| Anl A,<byte> | A=A and <byte> | V | V | V | V | 1 |
| Anl <byte>,A | <byte>=<byte>anl A | V | V | V | V | 1 |
| Anl <byte>,#data | <byte>=<byte>and #data | V | V | V | V | 1 |
| Orl A,<byte> | A=A or <byte> | Accumulator Only | | | | 1 |
| Orl <byte>,A | <byt>=<byt>orl A | V | V | V | | 1 |
| Orl <byte>,#data | <byte>=<byte> or #data | Data Pointer Only | | | | 2 |
| Xrl A,<byte> | A=A xor<byte> | Accumulator Only | | | | 1 |
| Xrl<byte>,A | <byt>=<byt>xor A | V | V | V | | 1 |
| Xrl <byte>,#data | <byte>=<byte>xor #data | Accumulator and B Only | | | | 4 |
| CLR A | A=00h | Accumulator only | | | | 1 |
| CPL A | A= not A | Accumulator only | | | | 1 |
| RL A | Rotate A left 1 bit | Accumulator only | | | | 1 |
| RLC A | Rotate A left trough Carry | Accumulator only | | | | 1 |
| RR A | Rotate A right 1 bit | Accumulator only | | | | 1 |
| RRC | Rotate A right trough carry | Accumulator only | | | | 1 |
| SWAP A | Swap nibbles in A | Accumulator only | | | | 1 |Logical operations generally include four things, namely AND operations, OR operations, EX-OR operations and NOT operations. MCS51 can only carry out three types of existing logical operations, namely ANL (AND Logical) instructions for AND operations, ORL (OR Logical) instructions for OR operations, CPL (Complement bit) for NOT operations.
The Carry bit in the PSW is treated as an 'accumulator bit', thus AND and OR operations are performed between the bit stored in the Carry bit and any of the 256 data bits discussed above. Examples of these instructions are:
ANL C,P1.1
ANL C,/P1.2The ANL C,P1.1 instruction ANDs the value of the Carry bit with the value of Port 1 bit 1 (P1.1), and the result of the operation is stored in the Carry bit. The ANL C,/P1.1 instruction is exactly the same as the previous instruction, except that before being ANDed, the value of P1.1 is reversed (complemented) first, if the value of P1.1 = '0' then what is ANDed with the Carry bit is '1', and vice versa. The same thing applies to the ORL instruction.
The CPL instruction is used to invert (complement) the value of all 256 bits of data discussed above. For example:
CPL C
CPL P1.0CPL C will invert the binary value in the Carry bit (don't forget that the Carry bit is one of the bits in the 256 bits discussed above, namely bit number $E7 or PSW.7).
5. Jump Instructions
Basically, the program is executed instruction by instruction, meaning that after completing one instruction, the microcontroller immediately executes the next instruction. For this purpose, the microcontroller is equipped with a Program Counter that regulates the sequential fetching of instructions. However, a program that only works sequentially is not very meaningful. For this purpose, the microcontroller is equipped with instructions to regulate the program flow.
In general, the instruction groups used to regulate program flow consist of JUMP instructions (equivalent to the GOTO statement in Pascal), instructions to create and use subroutines/modules (equivalent to PROCEDURE in Pascal), conditional JUMP instructions (equivalent to the IF .. THEN statement in Pascal). In addition, there are also PUSH and POP instructions that can affect program flow.
Since the Program Counter is the only register in the microcontroller that controls the program flow, the group of program control instructions discussed above all change the value of the Program Counter, so that when this group of instructions is executed, the value of the Program Counter will not be consecutive from the value of the previous instruction.
In addition to the instructions above, the Program Counter value can also change due to the influence of hardware, namely when the microcontroller is reset or receives an interrupt signal from an input/output device. This will be discussed in detail in another section.
The microcontroller executes instruction after instruction, after completing one instruction the microcontroller immediately executes the next instruction, this is done by increasing the Program Counter value by the number of bytes that make up the instruction being executed, so that when the instruction in question is executed the Program Counter always stores the program memory number that stores the next instruction.
When the microcontroller executes a group of JUMP instructions, the Program Counter value that is sequentially set according to the program flow is replaced with the new program memory number desired by the programmer.
The MCS51 microcontroller has 3 types of JUMP instructions, namely the LJMP (Long Jump) instruction, the AJMP (Absolute Jump) instruction and the SJMP (Short Jump) instruction. The work of these three instructions is exactly the same, namely giving a new value to the Program Counter, the speed of executing these three instructions is also exactly the same, namely requiring 2 instruction periods (if the MCS51 works at a frequency of 12 MHz, then this instruction is executed in 2 micro-seconds), which differ in the number of bytes forming the instruction, the LJMP instruction is formed with 3 bytes, while the AJMP and SJMP instructions are sufficient with 2 bytes.
LJMP Instructions
The code for the LJMP instruction is $02, the new program memory number is expressed in 16-bit binary, thus this instruction can reach all of the 64 KiloByte MCS51 program memory. The LJMP instruction consists of 3 bytes, which can be expressed in the general form 02 aa aa, the first aa is the program memory number bits 8 to 15, while the second aa is the program memory number bits 0 to 7.
The use of LJMP instructions can be learned from the following program excerpt:
LJMP TugasBaru
...
ORG $2000
TugasBaru:
MOV A,P3.1In the program snippet above, ORG is a command to the assembler so that the next assembler works on the program memory number mentioned behind ORG (in this case, ask the next assembler to work on program memory number $2000). NewTask is called LABEL, which is a means for the assembler to mark/name the program memory number. Thus, in the program snippet above, program memory number $2000 is named NewTask, or it can also be said that NewTask is worth $2000. (Note: LABEL is written at least one letter more to the left than the instruction, meaning LABEL is written after pressing the Enter key, but the instruction is written after pressing the Enter key, then followed by 1 space key or the TAB key).
Thus, the LJMP NewTask instruction above has the same meaning as LJMP $2000 which the assembler will translate into 02 20 00 (hexadecimal).
AJMP Instructions
The new program memory number is stated in 11-bit binary, thus this instruction can only reach one area of MCS51 program memory as far as 2 KiloByte. The AJMP instruction consists of 2 bytes, the first byte is the code for the AJMP instruction (00001b) combined with the program memory number bits 8 to 10, the second byte is used to state the program memory number bits 0 to 7.
Here is a program excerpt to explain the use of the AJMP instruction:
ORG $800
AJMP DaerahIni
AJMP DaerahLain
ORG $900
DaerahIni:
. . .
ORG $1000
DaerahLain:
. . .The above program fragment starts at program memory number $800, thus the instruction AJMP ThisArea can be used, because the memory number $800 (where the instruction AJMP ThisArea is located) and LABEL ThisArea are located in the same 2-KiloByte program memory area. (It is said to be located in the same 2-KiloByte program memory area, because bits 11 to 15 of the memory number are the same).
But AJMP OtherArea will be wrong by the Assembler, because OtherArea located in program memory number $1000 is located in another 2 KiloByte program memory area.
Because AJMP instruction consists of only 2 bytes, while LJMP instruction consists of 3 bytes, then using AJMP instruction is more memory-efficient than LJMP. However, because AJMP instruction range is only 2 KiloByte, its use must be careful.
The program memory of the AT89C1051 and AT89C2051 microcontroller ICs is only 1 KiloByte and 2 KiloByte respectively, thus the programs for the two microcontrollers above do not need to use LJMP instructions, because the programs written cannot possibly span more than 2 KiloByte of program memory.
SJMP Instructions
The program memory number in this instruction is not stated as the actual program memory number, but as a 'relative shift' to the Program Counter value when this instruction is executed.
The relative shift is expressed by 1 byte of 2's complement number, which can be used to express values between --128 and +127. Minus values are used to express shifts to previous instructions, while positive values express shifts to subsequent instructions.
Although the range of the SJMP instruction is only --128 to +127, it is not limited by the 2 KiloByte program-memory area definition that limits the AJMP instruction.
ORG $0F80
SJMP DaerahLain
. . .
ORG $1000
DaerahLain:In the above program fragment, the program memory $0F80 is not located in the same 2 KiloByte program memory area as $1000, but the SJMP instruction OtherArea can still be used, as long as the distance between it and the OtherArea LABEL is not more than 127 bytes.
Sub-routine instructions
Instructions for creating and using subroutines/program modules, besides involving the Program Counter, also involve the Stack which is managed by the Stack Pointer Register.
Sub-routine is a piece of program that for various reasons is separated from the main program. Parts of the main program will 'call' (CALL) the sub-routine, meaning the microcontroller temporarily leaves the main program flow to work on the instructions in the sub-routine, after finishing the sub-routine the microcontroller returns to the main program flow.
The only way to create a subroutine is to put a RET instruction at the end of the subroutine program segment. The subroutine program is 'called' with the ACALL or LCALL instruction.
So that the microcontroller can continue the main program flow, when receiving an ACALL or LCALL instruction, before the microcontroller goes to work on the sub-routine, the current Program Counter value is first stored in the Stack (the Stack is a small part of the data memory used to store the Program Counter value automatically, the work of the Stack is controlled by the Stack Pointer Register).
Next, the microcontroller executes the instructions in the sub-routine until it encounters the RET instruction which functions as the closing of the sub-routine. When receiving the RET instruction, the original value of the Program Counter before executing the sub-routine stored in the Stack is returned to the Program Counter so that the microcontroller can continue working in the main program flow.
The ACALL instruction is used to 'call' a sub-routine program in the same 2 KiloByte program-memory area, equivalent to the AJMP instruction discussed above. While the LCALL instruction is equivalent to the LCALL instruction, which can reach the entire 64 KiloByte program-memory of the MCS51 microcontroller. (But there is no SCALL instruction equivalent to the SJMP instruction).
Programs for the AT89C1051 and AT89C2051 do not need to use the LCALL instruction.
The RET instruction is used to end a sub-routine program, besides that there is also the RETI instruction, which is an instruction used to end the Interrupt Service Routine Program, which is a kind of sub-routine program that is run by the microcontroller when the microcontroller receives an interrupt request signal.
Note: When the microcontroller receives an interrupt request signal, it will do the equivalent of the LCALL instruction to execute the Interrupt Service Program from the interrupt signal in question. In addition, the microcontroller will also temporarily 'turn off' the interrupt service mechanism, so that subsequent interrupt requests will not be served. When it receives a RETI instruction, the interrupt service mechanism is reactivated and the microcontroller will do the equivalent of the RET instruction.
Conditional Jump Instruction
Conditional Jump instructions are core instructions for microcontrollers, without this group of instructions the program written is meaningless. These instructions, in addition to involving the Program Counter, also involve certain conditions that are usually recorded in certain bits collected in certain Registers.
Specifically for the MCS51 microcontroller family which has the capability to handle operations at the bit level, the conditional jump instructions in the MCS51 are also associated with the MCS51's bit operation capability.
The new program memory number to which the instruction is to be addressed is not specified by the actual program memory number, but is specified by a 'relative shift' to the Program Counter value when this instruction is executed. This method is also used for the SJMP instruction.
JZ/JNZ Instructions
The JZ (Jump if Zero) and JNZ (Jump if not Zero) instructions are conditional JUMP instructions that monitor the value of Accumulator A.
MOV A,#0
JNZ BukanNol
JZ Nol
. . .
BukanNol:
. . .
Nol :
. . .In the example program above, MOV A,#0 makes A zero, this causes the JNZ BukanZero instruction to never be executed (JNZ means Jump if the value of A <> 0, this condition is never met because when this instruction is executed the value of A = 0), while the JZ Zero instruction is always executed because the condition is always met.
JC/JNC Instructions
The JC (Jump on Carry) and JNC (Jump on no Carry) instructions are conditional jump instructions that monitor the value of the Carry bit in the Program Status Word (PSW).
The Carry bit is a bit that is widely used for bit operations, to save program memory usage, 2 special instructions are provided to check the condition of the Carry bit, namely JC and JNC. Because the bit to be checked is certain, namely the Carry bit, this instruction is formed with only 2 bytes, thus saving more program memory.
JC Periksa
JB PSW.7,PeriksaThe results of the two instructions above are the same, namely MCS51 will JUMP to Check if the Carry bit is '1' (remember the Carry bit is the same as PSW bit 7). Although the same, the JC Check instruction is shorter than the JB PSW.7, Check instruction, the first instruction is formed with 2 bytes and the second instruction 3 bytes.
The JBC instruction is the same as the JB instruction, except that if it turns out that the bit being checked is indeed '1', besides the MCS51 will JUMP to another desired instruction, the MCS51 will zero the bit that has just been checked.
JB / JNB / JBC Instructions
The JB (Jump on Bit Set) instruction, the JNB (Jump on not Bit Set) instruction and the JBC (Jump on Bit Set Then Clear Bit) instruction are conditional Jump instructions that monitor the values of certain bits. Certain bits can be bits in the status register or the input pins of the MCS51 microcontroller.
Boolean Value Testing is done with the conditional JUMP instruction, there are 5 instructions used for this purpose, namely the JB (JUMP if bit set), JNB (JUMP if bit Not Set), JC (JUMP if Carry Bit set), JNC (JUMP if Carry Bit Not Set) and JBC (JUMP if Bit Set and Clear Bit) instructions.
In the JB and JNB instructions, one of the 256 bits will be checked, if its condition (false or true) meets the requirements, then the MCS51 will execute the instruction stored in the intended program memory. The program memory address is stated with a number relative to the current Program Counter value, and is simply stated with a 1 byte number. Thus this instruction consists of 3 bytes, the first byte is the operation code ($29 for JB and $30 for JNB), the second byte to state the bit number to be tested, and the third byte is a number relative to the destination instruction.
Examples of using the JB and JNB instructions are as follows:
JB P1.1,$
JNB P1.1,$The above instructions monitor the state of the MCS51 Port 1 bit 1 IC pin. The first instruction monitors P1.1, if P1.1 is '1' then the MCS51 will repeat this instruction, (the $ sign means if the condition is met, do the relevant instruction again). The next instruction does the opposite, namely as long as P1.1 is '0' then the MCS51 will be stuck on this instruction.
Process and test instructions
The conditional Jump instructions discussed above monitor conditions that have already occurred as recorded by the MCS51. There are two instructions that perform a process first and then monitor the results of the process to determine whether to Jump. The two instructions in question are the DJNZ instruction and the CJNE instruction.
DJNZ Instructions
The DJNZ (Decrement and Jump if not Zero) instruction is an instruction that will reduce the value of the general purpose register (R0..R7) or data memory by 1, and Jump if it turns out that after the reduction of 1 the result is not zero.
The following example is a program fragment to create a simple delay time:
MOV R0,#$23
DJNZ R0,$The MOV R0,#$23 instruction assigns a value of $23 to R0, then every time the DJNZ R0,$ instruction is executed, the MCS51 will reduce the value of R0 by '1', if R0 has not become zero then the MCS51 will repeat the instruction (the $ sign in this instruction means to execute this instruction again). While executing the 2 instructions above, all other work will be delayed, the delay time is determined by the value that is filled into R0.
CJNE Instructions
The CJNE (Compare and Jump if Not Equal) instruction compares two named values and the MCS will Jump if the two values are not equal!
MOV A,P1
CJNE A,#$0A,TidakSama
...
SJMP EXIT
;
TidakSama:
...The MOV A,P1 instruction reads the input value from Port 1, the CJNE A,#$0A,NotEqual instruction checks whether the Port 1 value stored in A is equal to $0A, if not then Jumps to NotEqual
Subject
- Characteristics of Machine Instructions
- Operand Types
- Operation Types
- Addressing Process
- Instruction Format.
1. Characteristics of Machine Instructions
These are special characteristics or unique properties that are possessed by instructions or operating codes in computer programming.
The functional set of different instructions that can be executed by a CPU is known as the CPU instruction set.
Elements of Machine Instructions:
- Operation Code (OP Code), specifies the operation to be performed. The Operation Code is in Binary Code form.
- Source Operand Reference , the operation can come from one source. The operand is the input of the operation.
- Result Operand Reference, the result of the operation/output of the operation.
- Next Instruction Reference , informs the CPU of the next instruction to be fetched and executed.
Operands and Results are stored in:
- Main Memory or Virtual Memory
- Register CPU
- I/O Device
2. Operand types
Addresses (will be discussed in addressing modes).
Numbers:
Integer or fixed point,Floating point,Decimal (BCD)
Characters :
ASCII, EBCDICLogical Data
Bila data berbentuk binary: 0 dan 1Types of computer operations
- Data transfer – conversion
- Arithmetic – input/output
- Logic – system control and control transfer
Instruction set operations for data transfer
- MOVE : move words or blocks from source to destination
- STORE : moves words from the processor to memory.
- LOAD : moves words from memory to the processor.
- EXCHANGE: change the content of the source to the destination.
- CLEAR / RESET : moves word 0 to the destination.
- SET : moves word 1 to the destination.
- PUSH : moves a word from the source to the top of the stack.
- POP : moves words from the top of the source
3. Types of Operations
- Arithmetic Operators, +(addition), – (subtraction), * (multiplication), / (division).
- Relational operators, express relations or comparisons between two operands, such as > (greater), = (greater or equal), <= (less than or equal), == (equal), != (not equal).
- Logical Operators, logically relate operands such as && (and), || (or), !(not).
Instruction set operations for logical operations
- AND, OR, NOT, EXOR
- COMPARE : performs logical comparison.
- TEST : test certain conditions.
- SHIFT : shifting the operand to the left or right causes a constant at the end of the bit.
- ROTATE : shifts the operand left or right with interlaced ends.
4. Addressing Process
Direct Addresing
- Direct Addressing, the price to be used is taken directly from another memory address.
- Advantages of Direct Addressing: The address field contains the effective address of an operand.
- Disadvantages of Direct Addressing. Limitation of address fields because the length of the address field is usually smaller than the length of the word.
Indirect Addresing
- Indirect Addressing can provide high flexibility in addressing a price.
- Advantages of Indirect Addressing. The space for addresses becomes large so that more addresses can be referenced.
- Disadvantages of Indirect Addressing. It requires double memory references in one fetch, thus slowing down the operation process.
Immediate Addresing
- Immediate Addressing, is very commonly used because the price to be stored in memory immediately follows the operation code in memory.
- Advantages of Immediate Addressing. No memory references other than the instructions required to obtain the operands, Saves instruction cycles so the overall process will be fast.
- Disadvantages of Immediate Addressing. The size of the number is limited by the size of the address field.
Introduction to Register Addressing
- This register addressing method is similar to the direct addressing mode.
- Advantages of Register Addressing. Small address fields are required in the instruction and no memory references are required. Access to the register is faster than access to memory, so the execution process will be faster.
- Disadvantages of Register Addressing. Address space becomes limited.
Register Indirect Addressing
The indirect register addressing method is similar to the indirect addressing mode. The difference is that the address field refers to a register address. The operand is located in the memory addressed by the register contents.
Displacement Addressing dan Stack Addresing
- Displacement Addressing, combines the capabilities of direct addressing and indirect register addressing. Three displacement models. Relative addressing, Base register addressing, Indexing, Relative addressing
- Stack Addressing. Stack is a linear array of locations = pushdown list = last-in-first-out. Stack is a block of locations that are reversed.
5. Instruction Format.
An instruction consists of several fields that correspond to elements in the instruction. The layout of an instruction is often referred to as the Instruction Format.
Types of instructions
- Data processing: Arithmetic dan Logic Instructions
- Data storage: Memory instructions
- Data Movement: I/O instructions
- Control: Test and branch instructions
Transfer data
- Specifies the location of the source operand and the destination operand.
- These locations can be memory, registers or the top of the stack.
- Sets the length of the transferred data.
- Sets the addressing mode.
CPU actions to perform data transfer
Moving data from one location to another.
When memory is involved:
- Sets a memory address.
- Performs transformation of virtual memory addresses to actual memory addresses.
- Initiates memory read/write.
Instruction Set, these instructions are fed to the microprocessor chip in the form of 8-bit binary numbers called Operational Code (Op-Code) along with data called operands. Writing a program with machine code is a long and tedious job, usually the program is written using the alphabet, then translated into a series of Op-Code & operands. The simplest form of translation is an assembler, which uses an assembly programming language.
In assembler language, each Op-Code has a mnemonic code, such as:
- LDA for load accumulator
- ADC for Add With Carry
- JMP for Jump, and so on.
Instruction sets can be grouped into three groups (subsets).
Data transmission that includes data movement between the CPU and memory locations, for example;
- Load the accumulator with the contents of memory (LDA).
- Saves the contents of the accumulator into memory (STA).
- Loads register X with the contents of memory (LDX).
Arithmetic & logic contains instructions for performing arithmetic & logic operations, for example:
- Adding two numbers with carry (ADC).
- Subtracting two numbers with carry (SBC).
- Operating AND on two numbers (AND).
- Perform EXOR on two numbers (XOR).
- Shift logically right (LSR).
- Arithmetic left shift (ASL).
Test & branch provides facilities for the microprocessor to perform a series of operations by jumping or branching to other parts of the program, for example
- Jump to subroutine (JSR).
- Branch if the result is negative (BMI).
- Branch if equal (BEQ).
Indirect Addresses and Indexes
Address Mode is the selection of data by PLC to be used in an instruction. Address mode is created by determining the instruction from the operand. So in this topic there will be terms: data, operand and instruction mode, which are defined as follows.
- DATA: numeric values used for computing. For example, if a PLC has a value of 4 in one memory address and a value of 2 in another memory address, and there is an ADD instruction for both addresses, then after the instruction is executed there will be a value of 4 and 2.
- OPERAND: symbols in an instruction. If there is an ADD instruction, then the data at the memory address is the same, but the location will be written with symbols.
- ADDRESSING MODE: describes the relationship between operands and data, namely how to use operands to retrieve the correct data.
1. Direct Addressing
In direct address mode, the memory address of the data is specified by the instruction. In the example in Figure 11.64, the address (2112) in the instruction goes directly to the address containing the data (85).
Figure 11.67: Direct Address Mode
2. Indirect Addressing
In indirect address mode, the address in the instruction serves as a reference point and is not a location containing the data to be addressed or retrieved. In other words, the memory address of the instruction contains the address of the location where the data is stored, as shown in Figure 11.65.
Figure 11.68: Indirect Address Mode
3. Indexed Addressing
Index address is an address mode for memory location reference that contains the "value" of the memory address + the value of the data stored in the index register. Index addresses are very useful for accessing elements in a data cluster. The address in the instruction does not change, but the index register value will change (increase), so that sequentially it will be able to access the data cluster location one by one. Imagine a postman who will deliver a letter to a dormitory resident. The dormitory address is still the same (instruction address), but the room address of each dormitory resident is different (index register). The postman must trace & see each room number in sequence, starting from the smallest number to the largest number (increase in the index register value) to find the right room. The room occupant is the data to be accessed.
Figure 11.69: Index Address Mode
4. Indirect Address Tracking & Indexed Addressing in Diagrams
Address mode is not an instruction, but can be used with PLC instructions. A common problem is selecting an offset or pointer value that is outside the "area" where the data is stored, causing errors. Some vendors provide the user with the freedom to define their own limits for the area where the data is stored.
PLC programs can be developed to solve more complex problems in the process of solving them. This can cause problems, when the program uses indirect addresses and index addresses on the ladder rank, where the ladder rank cannot function properly.
Tracking PLC programs containing indirect addresses is more difficult than those containing index addresses. Use the following hints if the program does not work properly.
- Make sure that the pointer is within the data memory area.
- The TND instruction can be used to stop scanning at a point in the ladder diagram containing the index address to be checked.
- Use the single-step option to scan one row at a time. Examine and analyze how the pointer changes the address flow.
- If the data elements to be stored are very large, and the storage memory uses a database structure, start tracking the disturbances from a small data set.
Summary
Some PLC definitions used to explain the meaning of PLC:
- PLC is a microcomputer system that people can use to control processes in industry.
- PLC is an industrial computer specifically designed to control manufacturing machines and systems in a wide variety of fields.
- PLC is a special electronic component based on one or more microprocessors that is used to control industrial machines.
Similarities between PLC and PC:
- has a motherboard,
- processor,
- memory and slots for expansion
PLC Architecture: Basically, PLC consists of an input section, a processing section, a memory section, lines for data (data bus) and addresses (address bus), and an output section.
Working principle: PLC work begins by initiating internal PLC programs, such as timers, notations, and so on. Then it will take input data obtained through the input interface. The data is then processed according to the instructions written in the program. The processing results will be channeled to the output through the output interface, and or to other parts according to the instructions.
Based on how it operates, PLCs are divided into 3:
- Rack or Address based System
- Tag Based System
- Soft PLC or PC based control.
The agreed PLC programming language standards are:
- Ladder Diagram (LD)
- Function Block Diagram (FBD)
- Structure Text (ST)
- Instruction List (IL)
- Sequential Function Charts (SFC)
All PLC programs are created based on basic logic sequences. Instructions are expressed through logical operations. The basic logic operations are: AND (describing a series circuit), OR (describing a parallel circuit) and NOT (describing an inverter circuit). From these three basics, other circuits can be developed which are a combination of the three.
Since PLC is usually used on AC voltage, we must be careful not to get electrocuted. Therefore, work safety procedures must be followed.
PLC maintenance includes hardware and software maintenance. In many cases, the most damage is to the input switches. Damage can be caused by component age, corrosion, or broken switch tongues.
To find damage to a PLC-assisted system, a tracing method is usually required. In this case it can be a block diagram, grouping or signal flow analysis. Software maintenance is usually the maintenance of a control program. Tracing can be done through control instructions, sub-routines, or direct or indirect addresses and indexes.
Question Practice
- What is a PLC? What do PLCs and personal computers (PCs) have in common?
- What are the advantages of PLC compared to computers?
- How PLC works, explain briefly in your own words.
- Name the PLC programming languages agreed upon by IEC?
- PLC works based on logic instructions. A PLC gets 2 inputs A and B, and output X. When both inputs are logic 1, the output will be logic 1. If one of the inputs is logic 0, the output will be logic 0. What logic operation is this?
Group task
Create a simple PLC program to control the lights and AC in your classroom. The lights will turn on when the sunlight starts to dim. Set the dimness level you want. Conversely, the lights will turn off automatically if the classroom is bright enough. Also set the brightness level of the light you want. The AC will be active if your classroom is hot and will turn off when the room temperature is cold. (Set the room temperature you want, for example between 23-30 degrees C). Also create a program so that the lights and AC both turn off a few moments after the room is empty and locked!
Getting to Know Subroutine Instructions
Subroutine is a group of instructions in a ladder diagram that is outside the main ladder program, which can be executed with a sub-routine instruction. So by using a subroutine instruction, a repetitive routine program can be executed repeatedly without having to rewrite the routine program in the main ladder diagram. For example, an automatic machine has a sequence of program lines that must be repeated several times in a machine cycle. The sequence can be programmed only once in a subroutine, which can be called if needed.
Figure 11.66: Jump to Subroutine Instruction
1. Subroutine Instruction Failure Tracking
If part of the ladder program is not working properly, perform the steps as recommended below:
- Use the always false (AFI) instruction on the input range containing MCR and JMP instructions, to narrow the MCR and JMP regions until a correct operation of the main program routine is found. AFI will set the range condition to be good again. So AFI will disable all instructions on the range.
- The TND or SUS instruction can be used to stop an MCR, JMP or JSR instruction after a branch, so that the input logic conditions can be evaluated. This is very useful if there is an error on the branch.
- Perform damage tracking on a chain using single-step mode.
- Use breakpoints in single-step mode to execute the ladder downwards, where breakpoints have been inserted in the ladder diagram.
To make tracking easier, make sure that:
- The MCR and/or JMP areas do not overlap.
- There is no backward jump that will cause the scan time to increase, when the program is re-scanned. If the scan time is more than 2.5 seconds, the processor will be damaged.
- JSR and SBR instructions have the same input parameter number.
- The JSR and RET instructions have the same return parameter number.
- The LBL and SBR instructions are the first input instructions in the range.
- The data type used in memory is the same/consistent with the data currently used.
Assembly Programming Interrupts
Interrupt is an event or incident that causes the microcontroller to pause for a moment to serve the interrupt. The program that is run when serving an interrupt is called an Interrupt Service Routine. The analogy is as follows, someone is typing a report, suddenly the telephone rings and interrupts the person so that they stop typing and pick up the telephone. After the telephone conversation which in this case is an analogy of the Interrupt Service Routine is finished, the person returns to continue typing.
Similarly, in a microcontroller system that is running its program, when an interrupt occurs, the program will stop for a moment, serve the interrupt by running the program at the address indicated by the vector from the interrupt that occurred until it is finished and then continue the program that was stopped by the interrupt. As seen in Figure 4.1, a program that should continue running straight, suddenly experiences an interrupt and must serve the interrupt first until it is finished before it continues its work.
Gambar 4.1 Interrupt
The process carried out by the microcontroller when serving an interrupt is as follows:
- The last instruction currently executing is completed first.
- The Program Counter (address of the currently executing instruction) is saved to the stack.
- Interrupt Status is stored internally
- Interrupts are serviced according to the interrupt ranking (see Interrupt Priority)
- The Program Counter is filled with the address of the interrupt vector (see Interrupt Vector) so that the microcontroller immediately executes the program located in the interrupt vector.
The program on the interrupt vector usually ends with the RETI instruction where at this time the process that occurs in the microcontroller is as follows:
- The Program Counter is filled with the address stored in the stack when the interrupt occurs so that the microcontroller continues the program at the location where the interrupt occurred.
- Interrupt Status is returned to the last condition before the interrupt occurred.
1. Enable Interrupt
In a condition it may also be necessary for a running program not to be interrupted, for that the 89C51 has five interrupts, each of which can be enabled or disabled one by one. The interrupt enable and disable settings are made in the Interrupt Enable Register located at address A8H.
YES
Disable all interrupts if this bit is clear. If this bit is clear, then regardless of the condition of other bits in this register, all interrupts will not be serviced, therefore to enable one of the interrupts, this bit must be set.
IS
Enable/disable Serial Port Interrupt, set = enable, clear = disable. If Serial Port Interrupt is active, an interrupt will occur whenever data enters or exits through the serial port that creates the RI (Receive Interrupt Flag) or TI (Transmit Interrupt Flag) Flag.
ET1
Enable/disable Timer 1 Interrupt, set = enable, clear = disable. If this interrupt is enabled then the interrupt will occur when Timer 1 overflows.
EX1
Enable/disable External Interrupt 1, set = enable, clear = disable. If this interrupt is enabled then the interrupt will occur when a low pulse occurs on INT1.
ET0
Enable/disable Timer 0 Interrupt, set = enable, clear = disable. If this interrupt is enabled then the interrupt will occur when Timer 0 overflows.
EX0
Enable/disable External Interrupt 0, set = enable, clear = disable. If this interrupt is enabled then the interrupt will occur when a low pulse occurs on INT0.
2. Status Interrupt
The interrupt statuses of the 89C51 are located in the TCON Register, namely;
- INT0: IE0 bit, cleared by hardware when an interrupt occurs in active level mode.
- INT1: Bit IE1, cleared by hardware when interrupt occurs in active level mode.
- Timer 0: Bit TF0, cleared by hardware when an interrupt occurs.
- Timer 1 : Bit TF1, cleared by hardware when interrupt occurs.
- Serial Port (TXD) : TI bit, clear by software
- Serial Port (RXD) : Bit RI, clear oleh software.
External Interrupt 0 and External Interrupt 1 can be set to be active level or active transition by changing the IT0 or IT1 bit in the TCON Register. External Interrupt will work actively at the level when the ITx bit (x = 0 for INT0 and x = 1 for INT1) is in low condition and work actively transition when the ITx bit is in high condition.
3. Interrupt Priority
In serving interrupts, the microcontroller works based on priorities that can be set in the Interrupt Priority Register.
- IP0 or PX0 for External Interrupt 0
- IP1 or PT0 for Timer 0 Interrupt IP2 or PX1 for External Interrupt 1 IP3 or PT1 for Timer 1 Interrupt IP4 or PS for Serial Interrupt
These bits will be set if the interrupt they control is set to high priority. A high priority interrupt can interrupt another lower priority interrupt, while a high priority interrupt itself cannot be interrupted by another interrupt.
If more than one interrupt with the same priority occurs simultaneously, the priority will be set by polling starting from:
- External Interrupt 0
- Timer 0 Interrupt
- External Interrupt 1
- Timer 1 Interrupt
- Serial Interrupt
4. Interrupt Vector
Interrupt Vector is a value stored in the Program Counter when an interrupt occurs so that the program will go to the address indicated by the Program Counter. When the program goes to the address indicated by the Interrupt Vector, the flags that are set due to the interrupt will be cleared except RI and TI.
The five interrupts and system reset of the 89C51 have their respective vectors which can be seen in Table 4.1.
Table 4.1 Interrupt Vector
| INTERRUPT | FLAG | ALAMAT VEKTOR |
|----------------------|------------|---------------|
| System Reset | RST | 0000H |
| External Interrupt 0 | I E0 | 0003H |
| Timer 0 | TF0 | 000BH |
| External Interrupt 1 | I E1 | 0013H |
| Timer 1 | TF1 | 001BH |
| Serial Port | RI atau TI | 0023H |Each vector address has a close distance so that a problem will arise if a fairly long Interrupt Service Routine is needed, for example, if External Interrupt 0 and Timer 0 are to be used in one system, then if the Interrupt Service Routine for External Interrupt 0 is placed at address 0003H and the Interrupt Service Routine for Timer 0 is placed at address 000BH, there will be an address clash between the two Interrupt Service Routines if the following trick is not carried out as seen in the following listing;
Listing 4.1
ORG 0000H
LJMP Start
ORG 0003H
LJMP Int0
ORG 000BH LJMP Timer0 ......
......
......
Start:
......
...... ;Main Program
......
Int0:
......
...... ;Int0 ISR ......
RETI
Timer0:
......
...... ;Timer 0 ISR ...... RETISo in this listing, when an interrupt occurs, the Program Counter still contains the value of the Interrupt Vector so that the program also jumps to that address, but because at that address there is already an instruction placed to jump to another label such as Int0 for the External Interrupt 0 Service Routine, there will be no address clash between the two Interrupt Service Routines.
An interrupt is a special request to the microprocessor to do something. When an interrupt occurs, the computer will stop what it is doing and do what the interrupter asked.
Understanding Interrupts in Assembly Programming
On the IBM PC and its compatibles, there are 256 interrupts numbered 0 to 255. Interrupt numbers 0 to 1Fh are provided by the ROM BIOS, an IC inside the computer that controls the basic operations of the computer. So if an interrupt occurs with the number 0-1Fh, then by default the computer will switch to the ROM BIOS and execute the program there. The program that handles an interrupt is called the Interrupt Handler.
1. Interrupt Vector
Each interrupt will execute its own interrupt handler based on its number. While the address of each interrupt handler is recorded in memory in the form of an array with each element size of 4 bytes. These four bytes are divided again, namely the first 2 bytes contain the offset code while the next 2 bytes contain the segment code of the relevant interrupt handler address. So the size of the array is 256 elements with each element size of 4 bytes. The total memory used is 1024 bytes (256 x 4 = 1024) or 1 KB and is stored in absolute memory locations 0000h to 3FFh. This 1 KB array is called the Interupt Vector Table. The values contained in this Interupt Vector Table will not be the same on one computer with another.
These 256 interrupts are divided into 2 types, namely:
- Interupt 00h - 1Fh (0 - 31) is a BIOS interrupt and standard on all computers whether using DOS operating system or not. The location of the Interupt Vector Table is at absolute address 0000h-007Fh.
- Interupt 20h - FFh (32 - 255) is a DOS interrupt. This interrupt only exists on computers that use the DOS operating system and its Interupt Handler is loaded into memory by DOS when DOS is used. The location of its Interupt Vector Table is at the absolute address 07Fh-3FFh.
2. Table BIOS Interrupt
| No. Interrupt | Nama Interrupt |
|---------------|------------------------|
| *00h | Divide By Zero |
| *01h | Single Step |
| *02h | Non MaskableInt(NMI) |
| *03h | Break point |
| 04h | Arithmatic Overflow |
| 05h | Print Screen |
| 06h | Reserved |
| 07h | Reserved |
| 08h | Clock Tick(Timer) |
| 09h | Keyboard |
| 0Ah | I/O Channel Action |
| 0Bh | COM 1 (serial 1) |
| 0Ch | COM 2 (serial 2) |
| 0Dh | Fixed Disk |
| 0Eh | Diskette |
| 0Fh | LPT 1 (Parallel 1) |
| 10h | Video Service |
| 11h | Equipment Check |
| 12h | Memory Size |
| 13h | Disk Service |
| 14h | Communication (RS-232) |
| 15h | Cassette Service |
| 16h | Keyboard Service |
| 17h | Printer Service |
| 18h | ROM Basic |
| 19h | Bootstrap Loader |
| 1Ah | BIOS time & date |
| 1Bh | Control Break |
| 1Ch | Timer Tick |
| 1Dh | Video Initialization |
| 1Eh | Disk Parameters |
| 1Fh | Graphics Char |** This Interrupt mark has been confirmed for use by the system for specific purposes, it cannot be changed by the programmer like the others.*
- DIVIDE BY ZERO: If division by zero occurs, the process will be stopped immediately.
- SINGLE STEP: To carry out / execute instructions one by one.
- NMI: Service for NMI (Non Maskable Interrupt), which is an interruption that cannot be prevented.
- BREAK POINT: If a program causes the overflow flag to become 1 then this interrupt will serve to prevent it and give an error signal.
3. DOS Interrupt Table
| No. Interrupt | Nama Interrupt |
|---------------|-----------------------------|
| 20h | Terminate Program |
| 21h | DOS Function Services |
| 22h | Terminate Code |
| 23h | Ctrl-Break Code |
| 24h | Critical Error Handler |
| 25h | Absolute Disk Read |
| 26h | Absolute Disk Write |
| 27h | Terminate But Stay Resident |In programming with assembler language we will use interrupts a lot to complete a task.
Definition of Register
In programming with Assembly language, you inevitably have to deal with what is called a Register. So what is actually meant by a register?
Getting to Know Assembly Programming Registers
Registers are part of the microprocessor's memory that can be accessed at very high speeds. In doing its work, the microprocessor always uses registers as intermediaries, so registers can be likened to the feet and hands of the microprocessor.
The registers used by the microprocessor are divided into 5 parts with different tasks, namely:
1. Register Segment
Registers included in this group consist of CS, DS, ES and SS registers, each of which is a 16-bit register. Registers in this group are generally used to indicate the address of a segment.
The CS (Code Segment) register is used to indicate the location of the active segment, while the SS (Stack Segment) register indicates the location of the segment used by the stack. These two registers should not be changed carelessly because it will cause chaos in your program later.
The DS (Data Segment) register is usually used to indicate the segment location where the data in the program is stored. Generally, the contents of this register do not need to be changed except in the resident program. The ES (Extra Segment) register, as the name implies, is a bonus register that does not have a special task. This ES register is usually used to indicate an address in memory, for example the video memory address.
In the 80386 processor there are additional 16-bit segment registers, namely FS <Extra Segment> and GS <Extra Segment>.
2. Pointer and Index Registers
Registers included in this group are SP, BP, SI and DI registers, each consisting of 16 bits. Registers in this group are generally used as pointers to a location in memory.
The SP (Stack Pointer) register which is paired with the SS (SS:SP) segment register is used to indicate the address of the stack, while the BP (Base Pointer) register which is paired with the SS (SS:BP) register records an address in memory where the data is located.
The SI (Source Index) register and the DI (Destination Index) register are usually used in string operations by directly accessing the memory addresses indicated by these two registers.
In the 80386 processor there are additional 32-bit registers, namely ESP, EBP, ESI and EDI.
3. General Purpose Register
Registers included in this group are AX, BX, CX and DX registers, each consisting of 16 bits. The 16-bit registers from this group have a characteristic, namely that they can be separated into 2 parts, each consisting of 8 bits, as in Figure 4.1. The suffix H indicates High while the suffix L indicates Low.
Figure 4.1. General purpose Register
In general, the registers in this group can be used for various purposes, however, there are also special uses for each of these registers, namely:
The AX register is specifically used in arithmetic operations, especially in division and subtraction operations.
The BX register is usually used to indicate an offset address of a segment.
The CX register is used specifically in looping operations where this register determines how much looping will occur.
DX register, used to hold the remainder of the 16-bit division result. On the 80386 processor there are additional 32-bit registers, namely EAX, EBX, ECX and EDX.
4. Index Pointer Register
The IP register is paired with CS (CS:IP) indicating the address in memory where the next instruction (command) will be executed. The IP register is also a 16-bit register. The 80386 processor uses the EIP register which is a 32-bit register.
5. Flags Register
As the name suggests, this Flags register shows the condition of a state < yes or no >. Because each state can only use 1 bit, then according to the number of bits, this Flags register is able to record up to 16 states. The flags found on the 8088 microprocessor and above are:
OF < OverFlow Flag >
If an OverFlow occurs in an arithmetic operation, this bit will be set to 1.
SF < Sign Flag >
If a signed number is used, this bit will have the value 1.
ZF < Zero Flag >
If the result of the operation is zero, this bit will be set to 1.
CF < Carry Flag >
If there is a borrow in a subtraction operation or a carry in an addition operation, this bit will be set to 1.
Figure 4.2. Layout of the 8088 Flags Register
PF < Parity Flag >
Used to indicate the parity of a number. This bit will have a value of 1 if the resulting number is an even number.
DF < Direction Flag >
Used in string operations to indicate the direction of the process.
IF < Interrupt Enable Flag >
The CPU will ignore interrupts that occur if this bit is 0.
TF < Trap Flag >
Used mainly for Debugging, with step by step operations.
AF < Auxiliary Flag >
Used by BCD operations, such as in the AAA command.
NT < Nested Task >
Used in 80286 and 80386 processors to maintain the flow of consecutive interrupts.
IOPL < I/O Protection level >
This flag consists of 2 bits and is used in 80286 and 80386 processors for protection mode.
The arrangement of each flag in the flags register can be seen in Figure 4.2. On the 80286 and 80386 processors and above, there are several additions to the flags register, namely:
PE < Protection Enable >
Used to enable protection mode. This flag will be 1 in protection mode and 0 in real mode.
MP < Monitor Coprosesor >
Used with the TS flag to handle the occurrence of a WAIT instruction.
EM < Emulate Coprosesor >
This flag is used to simulate an 80287 or 80387 coprocessor.
TS < Task Switched >
This flag is available on 80286 and above.
ET < Extension Type >
This flag is used to determine the type of coprocessor 80287 or 80387.
RF < Resume Flag >
This register is only available on 80386 processors and above.
VF < Virtual 8086 Mode >
When this flag is set to 1 during protection mode, the microprocessor will allow real mode applications to be run in protection mode. This register is only available on 80386 and above.
6. Understanding Registers in Digital Systems
Information consisting of a single bit is stored in a D flip-flop. A number of N bits of information forming one word with a length of N-bits can be stored in N D flip-flops. An example of a word with a length of 4-bits can be seen in Figure 4.27. The arrangement of flip-flops used to store data is called a register. In the configuration in the figure, the input data Di is entered into the register when the Write and Enable lines are high, synchronous with the clock.
The register contents can be read at the Qi output only when the Enable line is high, because the three-state buffer is electronically disconnected when Enable is low. We simplify the representation of the register to that shown in Figure 4.28.
Figure 4.28 Simplified 4-bit register
A shift register shifts the contents of one flip-flop to the next, and accepts input at the input end and spits out the contents at the output end, allowing them to be arranged in a sequence. Consider the shift register in Figure 4.29. It can be shifted left, shifted right, receive input in parallel, or left unchanged, all in synchrony with the clock. The parallel input and parallel read facilities enable the shift register to function as a serial-to-parallel or parallel-to-serial converter.
Figure 4.29 Shift register
Microcontroller Branching Instructions
ACALL addr11
| Siklus | Jumlah Byte | Instruksi | | | | | | | |
|--------|-------------|--------------|----|----|-----|-----|----|---|---|
| 2 | 2 | ACALL Addr11 | | | | | | | |
| Flag | | C | AC | F0 | RS1 | RS0 | OV | | P |
| | | | | | | | | | |Performs a jump to a subroutine pointed to by the address in addr11. The possible jumps are in an area of 2K bytes.
The process that occurs when this instruction is executed is as follows:
- The data at Program Counter + 2 which is the program address when returning from the subroutine is stored in the stack.
- Stack pointer increased by 2 times
- Perform a jump to the address pointed to by addr11 by filling the Program Counter with that address. The address filled into the Program Counter is only 11 bits so the maximum jump is only 2K bytes.
Example:
2000 Acall Lompatan1
…………
…………
Lompatan1
2100 Mov A,#00H The data in Program Counter + 2, namely 2002H, is stored on the stack where the high byte is stored at the address pointed by SP+1 and the low byte is stored at the address pointed by SP+2. If the previous SP position was at address 10H, the high byte, 20H will be stored at address 11H and the low byte, 02H is stored at 12H. Then the 11-bit data at jump address 1 is moved to the Program Counter.
LCALL addr16
| Siklus | Jumlah Byte | Instruksi | | | | | | | |
|--------|-------------|--------------|----|----|-----|-----|----|---|---|
| 2 | 3 | LCALL Addr16 | | | | | | | |
| Flag | | C | AC | F0 | RS1 | RS0 | OV | | P |
| | | | | | | | | | |Performs a jump to a subroutine pointed to by the address in addr16. The jumps that can be performed are in an area of 64K bytes.
The process that occurs when this instruction is executed is as follows:
- The data at Program Counter + 2 which is the program address when returning from the subroutine is stored in the stack.
- Stack pointer increased by 2 times
- Perform a jump to the address pointed to by addr16 by filling the Program Counter with that address. The address filled into the Program Counter is 16 bits so the maximum jump can reach 64K bytes.
Example:
2000 Lcall Lompatan1
…………
…………
Lompatan1
3000 Mov A,#00H The data in Program Counter + 2, namely 2002H, is stored on the stack where the high byte is stored at the address pointed by SP+1 and the low byte is stored at the address pointed by SP+2. If the previous SP position was at address 10H, the high byte, 20H, will be stored at address 11H and the low byte, 02H, will be stored at 12H. Then the 16-bit data at the jump address 1 is moved to the Program Counter, namely 3000H.
RIGHT
| Siklus | Jumlah Byte | Instruksi | | | | | | | |
|--------|-------------|-----------|----|----|-----|-----|----|---|---|
| 2 | 1 | RET | | | | | | | |
| Flag | | C | AC | F0 | RS1 | RS0 | OV | | P |
| | | | | | | | | | |Performs a jump to the address stored in SP and SP-1. This instruction is commonly used when returning from a subroutine called with the ACALL or LCALL instruction.
The process that occurs is as follows:
- The contents of the address pointed to by the stack pointer are moved to the high nibble of the Program Counter.
- Stack pointer decreased by 1
- The contents of the address pointed to by the stack pointer are moved to the low nibble of the Program Counter.
- Stack pointer decrements by 1.
Example:
2000 Lcall Lompatan1
2002 ……….…
…………
…………
Lompatan1
3000 Mov A,#00H
3002 Ret