A logic circuit can be built from several types of electronic components, the components in question are Logic Gate ICs, so that a complex logic circuit is formed, so from this complexity, students are required to learn how to simplify it.
Objective
- So that students understand the concept of compiling combinational digital circuits
- So that students are able to create combinational digital circuits
- So that students are able to simplify combinational digital circuits
The methods that can be used are:
- Karnaugh Map Method (Karnaugh Map) , is a simplification method using diagrams or graphics based on pattern recognition techniques. Karnaugh maps contain all possible outcomes of a combination digital circuit.
- Consensus Theorem Method , is a simplification method by eliminating terms or "consensus terms". With a pair of theorems whose variables appear in one complement term, then the variable appears in the original term and together leaves the selected variable and its complement.
- The Boelean Algebra method is a simplification method by defining the rules used to express binary number codes, for example "A OR B AND C" is written as "A+BxC".
PRACTICE - Standard Operating Procedure
- Prepare the equipment and materials needed.
- Implement the circuit schematic to be tested into the project board and confirm
- all connections and wiring are good and correct.
- Connect the adapter to the power outlet, then check the output from the adapter.
- Provide input with logic 0 by connecting the input to ground and 1 by connecting the input to ground.
- connect the input to the positive power supply (+5v)
- Perform step 6 according to the truth table requirements.
- Observe the changes in the LED and record the results in the lab results table.
- Repeat steps 2 - 6 for the other practical series.
- Finished.
EXPERIMENT 1
This video will answer the truth table in the circuit above (experiment 1)
Download Experiment Series 1 (77.8KB)
EXPERIMENT 2
This video will answer the truth table in the circuit above (experiment 2)
Download Experiment Series 2 (77.8KB)
Evaluation & Conclusion
Experiment 1
Based on the first experiment, the output produced is the same/identical to the truth table in the XOR circuit, so it can be concluded that the NAND gate combination circuit in experiment 1 is an equation of the XOR gate, where if both inputs are logically the same, the output will be logical 0, conversely if they are different, the output will be 1.
Experiment 2
Based on the second experiment, the output produced is the same/identical to the truth table in the XNOR circuit, so it can be concluded that the combination circuit of NOT, AND and OR gates in experiment 2 is an equation of the XNOR gate, where if both inputs are logically the same, then the output will be logical 1, otherwise if they are different then the output will be 0.
Sources & References
STMIK El Rahma Yogyakarta Module (By: Eko Yunianto / Ecko Anto. Blog: https://penakuliah.wordpress.com )
Tools
Ni Multisim (Electronic Workbench)
Understanding Digital Components
High-level digital circuit designs typically use a collection of gates packaged in the form of components rather than a single logic gate. This results in circuit complexity being reduced and modeling being simplified. Some of the components are discussed in the following sections.
1. Integration Level
So far we have discussed the design of combinational logic units. Since we are working with single gates, we are working at the small scale integration (SSI) level, which includes chips with 10 - 100 components. The definition of components here is different from the previous component, which refers to transistors and other discrete elements. In medium scale integration (MSI), the chip content ranges from 100-1000 components. Large scale integration (LSI) refers to chips with 1000-10,000 components, and very large scale integration (VLSI) contains even more components.
2. Multiplexer
A multiplexer or MUX (mutiplexer) is a component that has many inputs and 1 output. The block diagram and truth table of the 4-to-1 MUX are shown in Figure 2.21. The output F is the same as the input on the path selected by control inputs A and B. For example, if AB = 00, then the output F is the value at input D0 (either 0 or 1). The appropriate circuit for this MUX is shown in Fig.
Figure 2.21: Block diagram and truth table for a 4-to-1 MUX
When we design a circuit with MUX, we usually use a box shape like Figure 2.21, not a detailed shape like Figure 2.22. In this way, the circuit diagram becomes easier to understand.
Multiplexers can also be used to implement Boolean functions. Figure 2.23 shows the use of MUX as a majority function. Input data is taken directly from the truth table of the majority function, and the control inputs are connected directly to variables A, B, and C. The implementation of the function using MUX is to install 1 on the input line which is the minterm and fill in 0 for the others. Although some inputs are not used, the use of MUX for the implementation of Boolean functions, but there are also many Boolean functions that use it, because the design process and implementation become simpler.
Figure 2.22: Implementation of a 4-to-1 MUX with AND-OR
Figure 2.23: Implementation of an 8-to-1 MUX for the majority function
Another use case of a 4-to-1 MUX for a function with 3 variables is shown in Figure 2.24. The input data are taken from the set {0, 1, C, C^} and their grouping can be seen in the truth table. If AB = 00 then F = 0, regardless of the value of C, so we fill in 0 for input line 00 of the MUX. If AB = 01, then F = 1 regardless of the value of C, so we fill in 1 for line 01 of the MUX. If AB = 10 then F = C, because for C = 0 then F = 0 and for C = 1 then F = 1, so we fill in C for line 10 of the MUX. Finally for AB = 11, then F=C^ and we fill in line 11 of the MUX with C. In this way, we can implement a 3-variable function using a 2-variable MUX.
Figure 2.24: Implementation of a 4-to-1 MUX for a function with 3 variables
3. Demultiplexer
A demultiplexer or DEMUX is the inverse of a MUX. The block diagram for a 1-to-4 DMUX with input controls A and B and the corresponding truth table is shown in Figure 2.25. The DEMUX sends the input data D to one of the output lines Fi specified by the input controls. A typical 1-to-4 DEMUX circuit is shown in Figure 2.26. A DEMUX application is to send data from one source to one of a number of destinations, such as a button on an elevator to the nearest elevator. DEMUXes are not commonly used in the implementation of typical Boolean functions, although this can be done.
4 Decoders
The decoder logically translates the code into its meaning. At any one time only one output is 1, which is determined by the control input. The block diagram and truth table of a 2-to-4 decoder with control inputs A and B are shown in Figure 2.27. The corresponding decoder circuit is shown in Figure 2.28. The decoder can be used to control other circuits, and disable other circuits. For this reason, we add an Enable line that will produce all 0 outputs if Enable is set to 0, which is logically similar to a DEMUX with 1 inputs.
Figure 2.25: Block diagram and truth table for 1-to-4 DEMUX
Figure 2.26: 1-to-4 DEMUX circuit
One application of a decoder is to translate memory addresses into physical locations. Decoders can also be used to implement Boolean functions. Since each output line corresponds to a different minterm, the function can be implemented by ORing the outputs that correspond to true minterms. For example, Figure 2.29 is an implementation of the majority function using a 3-to-8 decoder. The unused outputs are left unconnected.
Figure 2.27: Block diagram and truth table of a 2-to-4 decoder.
Figure 2.28: 2-to-4 decoder circuit
5. Priority Encoder
An encoder translates a set of inputs into binary code, and can be understood as the opposite of a decoder. A priority encoder is a form of encoder that takes the order of inputs into account. Its block diagram and truth table are shown in Figure 2.30. The priority in this encoder means that the input Ai has a higher priority than Ai+1. The output is a value of 00,01,10, or 11 depending on the active input line with the highest priority. If no input is active, the output produces the default value A0 (F1F0 = 00).
Priority encoders are used to select from a number of devices competing for the same channel, for example if a number of users are simultaneously attempting to use the same computer system. A 4-to-2 priority encoder circuit is shown in Figure 2.31.
Figure 2.29: Implementation of the majority function with a 3-to-8 decoder
6. PLA
A programmable logic array (PLA) is a component that contains an AND matrix followed by an OR matrix. A PLA with 3 inputs and 2 outputs is shown in Figure 2.32. Three inputs A, B, and C and their complements are available as inputs to 8 AND gates that produce 8 multiplication terms. The outputs of the AND gates are connected to the inputs of all the OR gates that produce the function outputs F0 and F1. Programmable fuses are placed at each intersection of the AND and OR matrices. The PLA is programmed for a particular function by breaking the fuses in the matrix. When the fuse is broken at the AND gate, the input is connected to a logic 1 value. Likewise, if the fuse is broken at the OR gate, the input is connected to a logic 0.
As an example of how to use the PLA, we consider the implementation of the majority function using a 3 × 2 PLA (a function with 3 input variables × 2 outputs). For the sake of simplicity, the form shown in Figure 2.33 is used instead of 2.32. Note that a single line at the input of an AND gate represents 6 input lines, and a single line at each OR gate represents 8 input lines. The small dots at the junctions indicate where the connections are made. In Figure 2.32 the majority function uses only half of the PLA, and the rest can be used for other functions.
PLA is a component that has many uses as a general purpose digital circuit. The advantage of using PLA is that there are only a few inputs and outputs, and there are many logic gates between the inputs and outputs. The process of minimizing the number of connections in the circuit becomes important for modularizing the system into components. PLA is ideal for this purpose, and many programs automate the design of PLA for specific functions. To maintain the concept of modularity, PLA is often expressed as a black box as in Figure 2.34, and it is assumed that the contents of the PLA can be easily generated by a program automatically.
Figure 2.30: Block diagram and truth table of a 4-to-2 priority encoder
7. Use of PLA for Ripple-carry Summarizer
As another example of PLA implementation in digital circuits, we will design a circuit to add 2 numbers. Binary addition is similar to decimal addition by hand. Binary numbers are added from right to left, producing a result and a remainder (carry) at each bit. The previous two bits and the remainder are added at each bit position, so that the possibilities of each value and the result and remainder can be arranged as in Figure 2.35.
The truth table in Figure 2.35 describes an element called a full adder, and its symbol is shown next to it. A half adder can be used on the rightmost part of the adder which adds 2 bits and produces a sum and remainder. A full adder on the other hand adds 2 bits plus the remainder from the previous process and also produces a sum and remainder. A half adder is not used in this case to minimize the number of components. With 4 full adders installed in a cascade, a 4-bit binary adder can be produced, as shown in Figure 2.36. The most permanent adder uses a full adder by connecting the c0 input to 0.
Figure 2.31: 4-to-2 priority encoder circuit
It should be noted that the sum value cannot be calculated until the remainder of the previous full adder is calculated. The circuit is called a ripple carry adder because the true value seems to shift from right to left. Although the image shown looks like parallel, the bit addition is actually done serially from right to left. This is the weakness of this circuit. The full adder design approach using PLA is shown in Figure 2.37.
The PLA design approach is common, and computer-aided design tools for VLSI usually prefer PLA over MUX or others because of PLA's uniformity.
Figure 2.32: PLA 3 input 2 output
Figure 2.33: PLA simplification
Figure 2.34: PLA in black square form
Figure 2.35: PLA in black square form
Figure 2.36: Implementation of a 4-bit adder using a cascade full adder.
Figure 2.37: Full adder using PLA