IC or integrated circuit is a semiconductor electronic component that is a combination of hundreds or thousands of other components. The form of the IC is a solid silicon chip, usually black in color that has many legs (pins) so that its shape resembles a comb.
There are several types of IC based on its main components, namely TTL IC and CMOS IC. With this IC technology, it is very profitable, so that the circuit that previously took up a lot of space and was very complicated can be summarized in one IC chip.
IC TTL (Integrated Circuit Transistor Logic).
TTL IC is an IC that is widely used in digital circuits because it uses a relatively low voltage source, which is between 4.75 Volts to 5.25 Volts. The main components of TTL IC are several transistors combined to form two states (ON/FF). By controlling the ON/OFF conditions of transistors on digital ICs, various logic functions can be created. There are three basic logic functions, namely AND, OR and NOT.
CMOS ICs (Complementary Metal Oxide Semiconductor ICs)
Actually between TTL IC and CMOS IC have the same meaning, there are only a few differences, namely in the use of CMOS IC the power consumption required is very low and allows the selection of its source voltage which is much wider, namely between 3 V to 15 V. CMOS switching level is a function of the source voltage. The higher the voltage source will be as large as the voltage that separates the "1" and "0" states. The weaknesses of CMOS ICs include the possibility of component damage due to electrostatics and the price is more expensive. Keep in mind that all CMOS inputs must be grounded or connected to a voltage source.
Diode-Transistor Logic Diode Transistor Logic
As we said in the page on diode logic , the basic problem with DL gates is that they rapidly degrade logic signals. However, they do the job for one stage at a time, if the signal is re-amplified between the gates. NOR Gate Function
The above gate is a DL OR gate followed by an inverter as we saw in the page on resistor-transistor logic. The OR function is still performed by the diode. However, regardless of the number of logic 1 inputs, there must be an input voltage high enough to drive the transistor into saturation. Only if all inputs are logic 0 will the transistor hold. So, this circuit performs the NOR function.
The advantage of this circuit over the RTL equivalent is that the OR logic is done by diodes, not by resistors. Therefore there is no interaction between the different inputs, and any number of diodes can be used.
The downside to this circuit is the transistor's input resistor. Its presence tends to slow the circuit down, limiting the speed at which the transistor can switch states.
NAND Gate Function Image
Any logic 0 input will immediately pull the transistor base down and turn the transistor off, right? Remember that the base is 0.65 volts for the transistor input voltage? Diodes exhibit very similar forward voltages when they conduct current. Therefore, even with all inputs at ground, the transistor base will be around 0.65 volts, and the transistor can conduct.
To overcome this problem, we can add a series diode with the base lead of the transistor, as shown in the figure above. Now the forward voltage required to turn the transistor on is 1.3 volts. For even more insurance, we can add a second series diode and require 1.95 volts to turn the transistor on.
This way we can also be sure that temperature changes will not significantly affect the operation of the circuit. This circuit will work as a NAND gate. In addition, as a NOR gate with, we can use as many diode inputs as we might want without raising the threshold voltage.
Additionally, with no series resistor in the input circuit, there is less of a retarding effect, so the gate can switch states faster and handle higher frequencies.
The next obvious question is, can we rearrange things so that the NOR gate can avoid the resistor, and therefore switch faster too?
The answer is, Yes, there is. Consider the circuit shown above. Here we are using separate transistors connected together. Each has a single input, and therefore acts as an inverter in its own right.
However, with the collectors of the transistors connected together, a logic 1 applied to either input will force a logic 0 output. This is the NOR function. We can use multiple input diodes on one or both transistors, as with a DTL NAND gate. This will give us an AND-NOR function, and is useful in some circumstances. Such a construction is also known as an AOI (for AND-OR-Invert) circuit.
Diode Logic
Diode Logic takes advantage of the fact that an electronic device known as a diode will conduct electric current in one direction, but not in the other. In this way, the diode acts as an electronic switch.
For the circuit above is a basic diode OR and AND gate logic. We will assume that logic 1 is represented by 5 volts, and logic 0 is represented by ground, or zero volts. In this figure, if both inputs were left unconnected or both at logic 0, the Z output would also be held at zero volts by the resistor, and would thus be logic 0 as well. However, if either input were increased to +5 volts, the diode would be forward biased and would therefore conduct. This in turn would force the output all the way to logic 1. If both inputs were logic 1, the output would still be logic 1. Therefore, this gate correctly performs the OR function.
Using the same logic levels, but the diode is reversed and the resistor is set to pull the output voltage up to a logic 1 state. For this example, +V = +5 volts, although other voltages can easily be used. Now, if both inputs are ungrounded or if they are both at logic 1, the Z output will be at logic 1. If both inputs are grounded (logic 0), the diode will conduct and will pull the output to logic 0 as well. Both inputs must be logic 1 for the output to be logic 1, so this circuit is performing a logic AND function.
In both gates, we have made the assumption that the diode does not introduce any errors or losses into the circuit. This is not actually the case, a silicon diode will experience a forward voltage drop of about 0.65v to 0.7v when operating.
But we can get around this very nicely by specifying that any voltage above 3.5 volts should be a logic 1, and any voltage below 1.5 volts should be a logic 0. It is illegal in the system for the output voltage to be between 1.5 and 3.5 volts, this is an undefined voltage region.
Individual gates like the two above can be used to advantage in certain circumstances. However, when DL gates are cascaded, as shown to the left, some additional problems occur. Here, we have two AND gates, the outputs of which are connected to the inputs of an OR gate. It's very simple and seems reasonable. If we pull the inputs to logic 0, sure enough the output will be held at logic 0.
However, if both inputs of the AND gate were both at +5 volts, what would the output voltage be? The diode at the OR gate would immediately be forward biased, and current would flow through the AND gate resistor, through the diode, and through the OR gate resistor. If we assume that all the resistors are of the same value (usually, they are), they would act as a voltage divider and equally share the +5 volt supply voltage.
The OR gate diode will introduce a small loss into the system, and the output voltage will be about 2.1-2.2 volts. If both AND gates have logic 1 inputs, the output voltage can increase to about 2.8-2.9 volts. Obviously, this is in the "forbidden zone," which should not be allowed.
If we go one step further and connect the outputs of two or more of the other AND gate structures, we lose all control over the output voltage; there will always be a reverse-biased diode somewhere blocking the input signal and preventing the circuit from operating properly. This is why Diode Logic is only used for single gates, and only under certain circumstances.
CMOS Logic
CMOS logic is a new technology, based on the use of complementary MOS transistors to perform logic functions with almost no current required. This makes these gates very useful in battery-powered applications.
The fact that they will work with supply voltages as low as 3 volts and as high as 15 volts is also helpful.
The CMOS gates are all based on the basic inverter circuit shown to the left. Note that both transistors are enhancement-mode MOSFETs, one N-channel with the source grounded, and one P-channel with the source connected to +V.
Their gates are connected together to form the input, and their channels are connected together to form the output. The two MOSFETs are designed to have matched characteristics. Thus, they complement each other. When off, their resistance is effectively limited; when on, their channel resistance is about 200.
Since the gate is essentially an open circuit it draws no current, and the output voltage will be equal to either ground or the mains voltage, depending on how the transistor conducts.
When input A is ground (logic 0), the N-channel MOSFET is unbiased, and therefore has no enhanced channel within itself. It is open circuited, and therefore leaves the output path disconnected from ground.
At the same time, the P-channel MOSFET is forward biased, so it has an enhanced channel in itself. This channel has a resistance of about 200. Connect the output line to the V supply. This pulls the output up to + V (logic 1). When the A input is at + V (logic 1), the P-channel MOSFET is off and the N-channel MOSFET is on, So, this circuit correctly performs logic inversion, and at the same time provides active pull-up and pull-down, according to the output conditions.
This concept can be extended to NOR and NAND structures by combining inverters in a part-series, part-parallel structure. The circuit above is a practical example of a CMOS 2-input NOR gate.
In this circuit, if both inputs are low, both P-channel MOSFETs will be turned on, thus providing a connection to +V. Both N-channel MOSFETs will be turned off, thus there will be no ground connection.
However, if either input goes high, that P-channel MOSFET will turn off and disconnect the output from +V, while the N-channel MOSFET will turn on, thus grounding the output.
The structure can be reversed, as shown to the left.
Here we have a two-input NAND gate, where a logic 0 on either input will force the output to logic 1, but requires both inputs to be at logic 1 to allow the output to go to logic 0. This structure is less limited than its bipolar equivalent would be, but there are still some practical limitations. One is the combined resistance of the MOSFETs in series. As a result, CMOS totem poles are not made more than four inputs high. Gates with more than four inputs are built as cascading structures rather than single structures. However, the logic still applies. Even with these limitations, the totem pole structure still causes some problems in certain applications.
The pull-up and pull-down resistances at the output are never equal, and can change significantly as the input state changes, even if the output does not change logic state. The result is uneven and unpredictable rise and fall times for the output signal. This problem is addressed, and solved with the buffered B series, or CMOS gates.
The technique here is to follow the actual NAND gate with a pair of inverters. Thus, the output will always be driven by a single transistor, either P-channel or N-channel. Since they are as closely matched as possible, the output resistance of the gate will always be the same, and the signal behavior is therefore more predictable. One of the main problems with CMOS gates is their speed. They cannot operate very fast, due to their inherent input capacitance.
The B-series devices help to overcome these limitations to some extent, by providing uniform output current, and by switching the output states more quickly, even if the input signal changes more slowly. Note that we do not go into all the details of CMOS gate construction here.
For example, to avoid damage caused by static electricity, different manufacturers develop a number of input protection circuits, to prevent the input voltage from becoming too high. However, the protection circuits do not affect the logical behavior of the gate, so we will not go into details here.
One type of gate, shown to the left, is unique to CMOS technology. It is a bilateral switch, or transmission gate. It makes full use of the fact that the individual FETs in a CMOS IC are built to be symmetrical.
That is, the drain and source connections for each individual transistor can be interchanged without affecting the performance of either the transistor itself or the circuit as a whole. When N- and P-type FETs are connected as shown here and their gates are driven from complementary control signals, both transistors will be turned on or off together, rather than alternately.
If they are both off, the signal path is essentially an open circuit - there is no connection between the input and output. If they are both on, there is a very low resistance connection between the input and output, and the signal will pass. What is really interesting about this structure is that the signal controlled in this way does not have to be a digital signal. As long as the signal voltage does not exceed the power supply voltage, even analog signals can be controlled by this type of gate.
Note: cmos voltage 3V to 15V. cmos ic input must be grounded, when I lifted the jumper cable to connect it to the voltage source, it turned out that the LED was already on first, even though one of the inputs from the gate had not been connected to gnd or vcc, but it is different with the cmos ic, when the input jumper switch has not been connected anywhere then there is no reaction to the indicator,
Difference Between CMOS and TTL ICs
TTL stands for Transistor-Transistor Logic.It is a classification of integrated circuits. The name comes from the use of two bipolar Junction Transistors or BJTs in the design of each logic gate.
CMOS (Complementary Metal Oxide Semiconductor) is also another IC classification that uses Field Effect Transistors in the design.
The main advantage of CMOS chips over TTL chips is the greater density of logic gates in the same material.
A single logic gate in a CMOS chip may consist of as few as two FETs while a logic gate in a TTL chip may consist of a large number of parts as additional components such as resistors are required.
TTL chips tend to consume more power than CMOS chips especially at rest.
The power consumption of CMOS chips can vary depending on several factors.
One of the major factors in the power consumption of a CMOS circuit is the clock rate, with higher values resulting in higher power consumption.
Typically, a single gate in a CMOS chip can consume about 10nW while an equivalent gate in a TTL chip can consume about 10mW. That is a large margin, which is why CMOS chips are preferred in mobile devices with limited resources such as batteries.
Slightly more delicate than TTL chips, they require special handling as they are susceptible to electrostatics.
Most technicians often do not realize that what causes their devices to be damaged is actually touching the CMOS type IC with their hands without a wire strap.
The superiority of CMOS chips has pushed TTL chips further back.
CMOS chips that emulate TTL logic also became popular and slowly replaced TTL chips. These chips have names similar to TTL, so users can easily identify them.
CMOS IC supply voltage between 3 volts to 15 volts.
The CMOS IC input must be grounded, when I lifted the jumper cable to connect it to the voltage source, it turned out that the LED was already on, even though one of the gate inputs had not been connected to GND or VCC, but it is different with the CMOS IC, when the input jumper switch has not been connected anywhere, there is no reaction to the indicator.