FET works / depends on the electric field generated by the application of an input voltage to the gate terminal. This field will control the width of the channel where conduction occurs between the drain and source.
1. FET Types:
- junction FET (junction FET = JFET)
- Metal-oxide-semiconductor FET (MOSFET)
- Power FETs such as VMOS.
FET Family Symbols - JFET (a); reduction MOSFET (b); increase MOSFET (c); VMOS (d)
2. FET as a switch
FET circuit as a switch
FET Characteristic Measurement Curve
1. Specific Learning Objectives
Participants must be able to:
- Assembling the components
- Analyzing components by measuring electrical quantities
- Creating a FET Characteristic Curve Graph.
2. Tools and Materials
Tools:
- Experimental board 1 piece
- 2 pcs 0-30V DC power supply
- 1 piece of milliammeter
- Sufficient connecting wire
Material:
- FET MPF 102 1 piece
- Sufficient graph paper.
3. Occupational Safety
- Be careful when assembling components
- Be careful in measuring
- Observe the measurements carefully.
4. Information
This experiment is intended to measure the voltage function UGS, current function Ig and current function Id, voltage function UDS, which are then displayed in the FET characteristic curve.
5. Work Steps
Make a network like the following picture:
Working Circuit Diagram
- Provide a power supply voltage of 0.5 Volts to the GS leg.
- Measure and record the magnitude of the ID current.
- Assignment: Complete the following table!
| U DS UGS | 0 V | 3 V | 5 V | 7 V | 10 V | 12 V | 15 V | |
|------------|-----|-----|-----|-----|------|------|------|---------|
| 0,5 | | | | | | | | ID (mA) |
| 0 | | | | | | | | |
| -0,5 | | | | | | | | |
| -1 | | | | | | | | |
| -1,5 | | | | | | | | |
| -2 | | | | | | | | |
| -3 | | | | | | | | |Based on the ID measurement results written in the table above, make a graph!
6. Answer Sheet
| U DS UGS | 0 V | 3 V | 5 V | 7 V | 10 V | 12 V | 15 V | |
|----------|-----|-----|------|------|------|------|------|---------|
| 0,5 | 0 | 0 | 0,3 | `O,8 | 1,5 | 4 | 4,7 | ID (Ma) |
| 0 | 0 | 0,9 | 1,6 | 2,2 | 3,5 | 4 | 4,7 | |
| -0,5 | 0 | 1,2 | 1,5 | 2 | 3 | 4 | 4,7 | |
| -1 | 0 | 1 | 1,3 | 1,7 | 2,5 | 4 | 4,5 | |
| -1,5 | 0 | 0,8 | 1,25 | 1,7 | 3 | 4 | 4,4 | |
| -2 | 0 | 0,7 | 1,2 | 1,7 | 3 | 4 | 4,6 | |
| -2,5 | 0 | 0,6 | 0,9 | 1,2 | 1,8 | 4 | 4.6 | |
| -3 | 0 | 0,5 | 0,9 | 1,6 | 2,8 | 4 | 4,5 | |7. Graphic image
FET Characteristics Graph
Basic Properties of FET
In Figure 3, it shows that the more negative the UGS, the smaller the ID current.
x Under normal conditions, the JFET always works at a characteristic section that is almost horizontal, or in other words, the JFET is operated with a drain voltage that is greater than the UK (Knee voltage) but smaller than the breakdown voltage.
Fig.3 Basic Circuit Making JFET Characteristics
Fig.4 Analyzing the Properties of the JFET Curve. N Channel
See figure 4, then Uds must be made larger than 4 Volts but smaller than 30 V. And likewise UGS must be between (0 to 4V)
The knee voltage for the top characteristic curve is called the pinch off voltage (Up), so if the data sheet says Up = 4 Volts, the JFET must be operated with a UDS voltage greater than 4 Volts.
From the curve image 1-b, we can see that at a voltage of UGS = -4 V the drain current is almost = 0. The UGS value that causes ID = 0 is called Gate Source Cut Off Voltage (UGS = Off).
Up and UGS (off) have an important relationship, namely the absolute value of Up = the absolute value of UGS (off), only the sign is different;
- Up = 4 V
- UGSoff = -4 V
This applies to all JFETs and it should be remembered that on the JFET data sheet only the (UGS off) value will be mentioned.
The top characteristic curve is made with gate voltage = 0, this condition is also called the Sharted Gate Condition, because it is the same as the condition where the gate is shorted to the source.
The drain current along the nearly horizontal section is considered the same, even if the drain voltage is varied and in the data sheet this current is called Idss.
In the curve image it appears that the distance between the horizontal lines is not the same even though the difference in UGS for each line remains 1 Volt. This is known as Square low behavior and this is one of the advantages of FET over BJT Transistor.
FET Specification Data (Limit Price)
The limit price referred to in this problem is a description of the data on Fet and Mosfet components that must be met and must not exceed the maximum limit, and must not be much lower than the minimum limit.
The limit prices include: VDS mak, ID mak, Tj mak, PTOT mak, VGS (off) / VGTH, IDSS / ID on, GFS, RDS, CISS, CRSS.
Information about limit prices and how to use them, please study the information and explanation of the table below:
By knowing the limit price data, we can replace the fet with another Type, as long as the limit price data and type are the same.
Explanation of Tables
To understand the information contained in the table, a detailed explanation is provided below.
Explanation of the symbols & codes used
Packaging Sketch Diagram & Foot Identification
The packaging sketches have been grouped, where possible using the "TO" or "SOT" standard, with each leg or terminl numbered. There may be slight variations in the lengths between manufacturers using standard packaging, but they do not deviate much from the given dimensions. Over time, packaging styles have evolved to meet the demands of new technologies and new production. Suffixes have been added to packaging styles to indicate variants, and styles have even been renamed, for example TO3 has become TO204 and TO92 has become TO226. The format of the legs has also changed, where previously it was common to find components in TO92 packaging whose leg arrangement was designed in the TO 18 style. This style no longer follows the inline leg arrangement with the legs formed in the TO 18 format. This allows for differences between the physical and the illustrations in this appendix.
The connection details are described in a unique way that allows the user to compare the leg arrangements of various components to select, compatibility. The basic FET component or Has three connections, therefore only six possible leg arrangement combinations. The table on the next page explains the meaning of the capital letters that refer to the six basic leg arrangement variations. Each sketch shows leg 1 and the following legs. The letter mark indicates leg 1 functions legs 1 , 2, and 3. The letter mark maintains the same order regardless of the package style. Several three-leg package styles and their connection details are fully illustrated below.
For four-terminal components, the combination number is increased greatly since the device pins now have alternate designations (Gate 1, Gate 2, Substrate, Case) in addition to the Source, Drain, and Gate described above. To keep variant numbers as manageable as possible, only the seven pins that have Gate 1 and Gate 2 are used in this book, and a few other pins that cannot be loaded using the method described below. Other pin arrangements with four or more pins are described using one of six letter designations (A through F) plus a lowercase letter to indicate the function of the additional pin (substrate, drain, gate, and k for case). The first letter in a multi-letter designation begins with pin 1 regardless of whether it is capitalized. The system also allows for describing devices containing multiple transistors. Several examples are illustrated on the opposite page.
There are some packaging styles or combinations of numbering with the arrangement of the legs that cannot be explained using the simple method above. In this case the packaging depiction has been explained by the marking of the legs.
For a given device number, the manufacturer may not fully describe the pin arrangement, and a package style that has four terminals may only be described by the marking of the three terminals that have been described. Very often, components tested for replacement have the wrong pin arrangement.
FET Leg/Electrode Layout Group Marking
FET Electrode / Leg Details
Foot Function Identification Letters:
- b = Substrate
- d = Drain
- g = Gate
- g1 = Gate 1
- g2 = Gate 2
- k = Case
- s = Source
| 1 | 2 | 3 | 4 | |
|---|----|----|----|----|
| A | d | g | s | - |
| B | d | s | g | - |
| C | g | s | d | - |
| D | g | d | s | - |
| E | s | d | g | - |
| F | s | g | d | - |
| G | | g1 | g2 | s |
| H | d | g2 | g1 | s |
| I | d | s | g1 | g2 |
| J | d | g1 | g2 | d |
| K | s | g1 | d | g2 |
| L | s | d | g2 | g1 |
| M | s | g2 | d | s |
| N | g1 | g | g | s |
| O | d | g | k | s |
| P | d | s | b | g |
| Q | d | g | b | s |For example, with a TO220 device, the tab (pin 4) is normally connected to pin 2, but it is connected to pin 3. Similarly, with a TO237 device, the tab may not be connected to the terminal because the tab is normally floating. Another anomaly may occur when a manufacturer states that the substrate or case of the device is connected to a pin that is designated as source, drain, or gate, while another manufacturer does not specify such a connection. The solution to such anomalies is beyond the scope of this book.
Electrical Properties of JFET
1. JFET parameters
Transconductance current relates output current to input voltage. For JFET is a graph against VGS for bipolar transistor transconductance curve is a graph of IC against VBE. For example by reading the prices of ID and VGS. In figure 1 we are shown in Figure Transconductance as shown in Figure 6a Generally the Transconductance curve of a JFET will look like Figure 6b.
Fig.5 Typical Set of Fast Curves
Fig.6 Transconductance Curve
For example, suppose a JFET has an IDSS of 4 mA and a UGS (off) of - 2 V. By substituting into equation (1) below;
With this equation we can calculate the drain current for any gate voltage in the active region. Many datasheets do not provide drain curves or transconductance curves. But you get the values of IDSS and UGS(off). By substituting these values into equation 1 you can calculate the drain current for any gate voltage.
The square law is another name for parabolic. This is why the JFET is often called a square law device. For reasons that will be discussed later, the square law property gives the JFET another advantage over bipolar transistors in circuits called mixers.
2. Normalized Transconductance Curve
We can rearrange equation ( 1 ) to obtain;
By substituting 0, 1/4, 1/2, 3/4, and 1 for UGS/UGS(off), we can calculate the corresponding ID/IDSS values of 1, 9/16, 1/4, 1/16, and 0. Figure 2c summarizes these results; this is true for all JFETs.
Here is a practical use of the curves in Figure 2c. To bias a JFET near the midpoint of its useful current range we need to generate an ID that is close to half the IDSS. The current ratio of 9/16 is close to the midpoint in drain current; therefore we can set the midpoint bias with a UGS close to it.
Given a MPF 102 with UGS(off) = -8 V, we must use UGS = -2 V to obtain a drain current close to half the maximum allowable drain current.
3. Transconductance
The quantity gm is called transconductance, defined as;
This says that transconductance is equal to the change in drain current divided by the corresponding change in gate voltage. If a 0.1 V change in gate voltage results in a 0.2 mA change in drain current.
Note: S is the symbol for the unit "siemens," originally denoted as "mho."
Figure 7 gives the meaning of gm in terms of the transconductance curve. To calculate gm at an operating point, we choose two adjacent points such as A and B on each side of point Q. The ratio of the change in ID to the change in UGS gives the value of gm between the two points. If we choose another pair of points on the upper part of the curve, namely C and D, we find a larger change in ID for a given change in UGS; therefore gm on the upper part of the curve has a larger value.
On the datasheet for a JFET you are usually given the value of gm at UGS = 0, which is the value of gm between points such as C and D in Figure 7. We will denote this value of gm as gmo to indicate that it is measured at UGS = 0.
By deriving the slope of the transconductance curve at other points, we can prove that each gm is equal to;
This equation gives gm at each operating point in relation to gmo on the data sheet.
Sometimes, gm is stated as gm (forward transconductance) or yfs (forward transmittance). If you can't find gm in the datasheet, look for gfs or yfs. For example, the datasheet for a 2N5951 gives gfs = 6.5 mjS at UGS = 0; this is equivalent to gmo = 6.5 mS = 6500 µS.
As another example, the 2N 5457 datasheet lists yfs = 3000 µS for UGS = 0, equivalent to gmo = 3000 µS.
Fig.7 Meaning of Transconductance Graph
4. Accurate UGS(off) Price
With calculus, we can derive the following useful formula:
This is useful because while IDSS and gmo are easy to measure with high accuracy, UGS(off) is difficult to measure; Equation ( 6 ) provides a way to calculate UGS(OFF) with high accuracy.
AC Drain Resistance
The resistance rds is the ac resistance from the drain to the source defined as;
Above the pinchoff voltage, the change in ID is small for a given change in UDS because the curve is nearly flat; therefore rds has a large value; typically between 10 kΩ and 1 MΩ. For example, if a change in drain voltage of 2 V produces a change in drain current of 0.02 mA,
Datasheets usually do not list rds values. However, they do provide the reciprocal specification, either gos (output conductance) or yos (output admittance). The drain resistance is related to the datasheet value as follows:
For example, the data sheet of a 2N5951 gives gos = 75 µS. By Equation (7a),
In addition, the 2N 5457 data sheet shows yos = 50 µS. By Equation (7b),
5. Drain-Source Resistance In On State
In the active region, Jfet works as a current source. But in the saturation region (drain voltage is less than Up) it works as a resistor. Why? Because in the saturation region, a change in drain voltage produces a proportional change in drain current. This is the reason the saturation region of a JFET operating in the ohmic region is defined as;
For example, if a change in drain voltage of 100 mV produces a change of 0.7 mA in the ohmic region
Example: A JFET has IDSS = 10 mA and gmo = 4000 µS . Calculate UGS(off), also calculate for gm at the bias midpoint.
Completion
With Equation ( 6 )
Now use equation (5) to obtain
6. FET Circuit Analysis
This chapter discusses the DC and AC operation of FETs. After deriving the formulas for bias and drain we discuss the use of buffers, AGC amplifiers and choppers.
7. Own bias
Figure 3-a shows self-bias, the most common way to bias a JFET. Drain current flows through Rp and RS, producing a drain-source voltage;
The voltage across the source resistance is due to the small gate current so it can be neglected, the gate terminal has a DC ground voltage, so that;
Therefore the potential difference between gate and source is;
This states that the drop across RS produces a bias voltage UGS. No external voltage source has to drive the gate, and this is why the circuit is known as a self-biased circuit.
Bias itself stabilizes the stationary (guiescent) operating point against changes in JFET parameters (quantities such as IDSS, gmo and so on). The idea is as follows:
a. Self-bias b. Circuit - Typical Q point
Suppose we substitute a JFET with one that has a gmo value twice the gmo value of the JFET. Then, the drain current in Figure 8-a will try to double. But because this drain current flows through RS, the gate-source voltage UGS becomes more negative and reduces the drain current that was previously increased.
In Figure 8-b the gate voltage is equal to one-quarter UGS(off) resulting in a drain current of one-half IDSS (approximation). Substituting these quantities into Equation 10 and solving for RS we obtain.
With Equation (6), we can simplify the equation to a useful equation;
If the gmo value of a JFET is known, take its reciprocal value, and we get the source resistance that sets the drain current equal to half the IDSS. Since gmo is always given precisely in the datasheet, Equation (12) provides a quick way to set the bias itself at the midpoint of the drain current.
EXAMPLE 1
2N 5457 in Figure 8-a has gmo = 5000 µS and IDSS = 5 mA. What price of RS produces a midpoint bias? What is the price of the UGS in question? UDS price?
COMPLETION 1
This source resistance produces a drain current of approximately 2.5 mA.
The gate-source voltage is;
The drain-source voltage is;
EXAMPLE 2
2N 5484 in Figure 9-b has gmo = 2.5 mS. What is the price of the RS that sets the midpoint bias?
COMPLETION 2
This resistor sets the ID close to half of the IDSS.
EXAMPLE 3
The datasheet for the 2N 5457 shows a minimum gmo of 1 mS and a maximum gmo of 5 mS. This means that if we were working with thousands of 2N 5457s we would find some with gmo as low as 1 mS and some with gmo as high as 5 mS. If a 2N 5457 were to be used in a large bias circuit, what value of RS would be required to set the midpoint bias?
COMPLETION 3
Here we have to compromise and use the average value, if we find the parameter values are very spread out it is best to use the geometric mean value. The geometric mean value for transconductance is given by the following equation.
By substituting the minimum and maximum prices of gmo 2N 5457 we get;
8. Self-bias graph
With equations (2), (6) and (10), we can derive the relationship between drain current, transconductance and source bias resistor. Figure 5 summarizes this relationship. This graph applies to all JFETs. The graph will help us determine the Q point of the self-biased circuit. The following examples show how.
EXAMPLE 4
A self-biased circuit uses a JFET with IDSS = 10 mA, RS = 100Ω, and gmo = 3000 µS. What is the drain current?
COMPLETION 4
Since IDSS is known to be equal to 10 mA,
EXAMPLE 5
A JFET has gmo = 8000 µS. What RS price do we need to get a quarter IDSS ID current.
COMPLETION 5
Given ID / IDSS = 0.25. In Figure 6, read the product of the relevant RS gmo, which is;
The source resilience required is;
EXAMPLE 6
In Figure 7, the first JFET has IDSS = 8 mA and gmo = 4000 µS. The second JFET has IDSS = 15 mA and gmo = 3300 µS. What is the drain current at each level?
COMPLETION 6
The first level has a product
In Figure 11, we read the current ratios in question.
9. Current source bias
Current source bias is the primary means of stabilizing the fast current against variations in FET parameters.
10. Two Catu
Figure 11-a shows how this is done if a split supply is available (positive and negative bias voltages). The bipolar acts as a current source and forces the JFET to have an ID equal to IC.
In Figure 7a, the bipolar transistor has an emitter current of.
The collector diode acts as a current source, hence it forces the drain current to be close to equal to IE. The conditions that must be met are;
This ensures negative UGS
Fig.12. Current source bias
Fig.12. Current source bias
The current source bias as in Figure 12-a fills it as well as possible, UGS and its variations are almost completely absent. The only significant variable is the UBE of the bipolar transistor. This variable varies slightly from transistor to transistor, and due to temperature changes. But this UBE change is only a few tenths of a volt. Therefore with a circuit like Figure 12-a we get an almost full (solid) ID value.
As a real example, the emitter current in Figure 12-b is;
This forces the drain current to approach a value equal to 1 mA. The drain to ground voltage is;
11. One Supply
If we do not have a negative bias voltage, we can still use a current source bias as shown in Figure 8-c. In this circuit the current divider (R! and R2) sets the voltage divider bias on the bipolar transistor. Almost all of the voltage across R2 arises through the resistance RE. This sets the emitter current to a value essentially independent of the JFET characteristics. Once again the collector diode acts as a current source forcing the drain current to be equal to the collector current. Note in particular that in Figure 8-c, do not change the position of the bottom of RG. Instead, connect it to the base of the diode; this is necessary to reverse-bias the collector of the diode.
Types of JFET Circuit Configurations
1. Common Source
In this configuration the input signal (Ui) is inserted between Gate and Source, while the load is installed between Drain and Source. So the principle scheme is like figure 2. In this circuit the input resistance is infinite and the output signal is 180o out of phase with the input signal (180° phase rotation occurs). This configuration is the most widely applied; it can be compared with a single emitter circuit.
Figure 13. Increasing Input Resistance by adding RG
Figure 14. Single Source Circuit (Common Source)
2. Single Door Configuration (Common Gate Configuration)
Common Gate Configuration as shown in Figure 15. In this configuration, the driving is done at the source, and the output signal is tapped from the Drain. There is no phase difference (phase rotation). The input resistance is low, because the signal source outputs current into the input circuit. Can be compared with the Single Base circuit. This circuit is rarely applied.
Figure 15. Single Door Series (Common Gate)
3. Common Drain Configuration
Common Drain Configuration as shown in Figure 16. In this circuit, the driving is done at the Gate, while the output is tapped from the source. The output signal voltage is small from the input signal voltage. There is no phase difference (phase rotation) between the input signal and the output, therefore the circuit is also called a Source Follower. The output resistance is low. Can be compared with an Emitter Follower.
Figure 16. Single Drain Circuit (Common Drain)
4. Examples of FET Use
4.1 FET as Analog Signal Amplifier
Due to the relatively small power level and very high input resistance, the FET itself has special properties for the INPUT LEVEL (FRONT AMPLIFIER) or FINAL AMPLIFIER.
DIRECT CURRENT AMPLIFIER, DIFFERENTIAL AMPLIFIER
FET As Analog Signal Amplifier
Information:
- T1 and T2
- SELECTION PAIR (IDENTIC TRANSISTORS)
- The source potential is located at the UGS ABOVE THE DIRECT PULSE VOLTAGE.
- (UE1 = UEZ)
- Namely: UA = VDM (UE1 - U); VDM ⤳ S
CURRENT SOURCE WITH FET CONDUCTION
I = constant current
Namely: - UGS = RS . I then I = - UGS / RS
4.2 FET as a Switch
FET As A Switch
The static physical properties correspond to a mechanical switch in the goods approach (better as a bipolar transistor):
- The FET switch on delivers a SMALL RESISTANCE between the drain and source which depends on the UGS.
- The FET off switch closes, GREATER RESISTANCE between drain and source which depends on UGS (UGS Up)
Switch characteristics (connectors): FET - Channel - n
Switch characteristics (connectors): FET
Connection requirements (channel -n, normal polarity)
Connection requirements (channel -n, normal polarity)
ANALOG SWITCH WITH J - FET
Analog Switch With JFET
STABLE MULTIVIBRATOR WITH MOSFET CLOSURE
Astable Multivibrator With MOSFET Shutdown
Source:
- Compiled by Drs. Herry Sudjendro
- Editor Drs. Asmuniv