About Microcontrollers & Flip-Flops (AMFF)

Substance:

  1. AT98551 INSTALLATION
  2. FLIP FLOP
  3. UP COUNTER
  4. INITIALIZATION OF 7 SEGMENT COMMON ANODE
  5. DOWN COUNTER
  6. COUNTER WITH MODULE
  7. TONE DECODER
  8. SET RESET (RS) FLIP-FLOP
  9. CLOCK SET RESET (RST) FLIP-FLOP 
  10. LOGIC GATE SIMULATION
  11. PROBE CHECKER
  12. DATA (D) FLIP FLOP
  13. TOGGLE (T) FLIP FLOP
  14. JK FLIP - FLOP
  15. SR FLIP - FLOP
  16. RING COUNTER REGISTER
  17. RING COUNTER (2)
  18. MICROCONTROLLER SOFTWARE

1. AT98551 Microcontroller Installation


AT89551 Microcontroller Configuration


Serial Port Configuration


Microcontroller Schematic

2. FLIP FLOP

One Short and Free Running (a stable). Illustrated as a box/line wave


Flip-Flop Signal

The length of a period or line or on or off depicted in the scheme above is dependent, meaning the longer the line, the longer the time span.


If the image on the side shows that from the OFF position to the ON position or vice versa, this takes time.

3. Up Counter (UP COUNTER)

Output Table

| Clock Ke- | Output |    |    |    | Desimal |
|-----------|--------|----|----|----|---------|
|           | Q4     | Q3 | Q2 | Q1 |         |
| 0         | 0      | 0  | 0  | 0  | 0       |
| 1         | 0      | 0  | 0  | 1  | 1       |
| 2         | 0      | 0  | 1  | 0  | 2       |
| 3         | 0      | 0  | 1  | 1  | 3       |
| 4         | 0      | 1  | 0  | 0  | 4       |
| 5         | 0      | 1  | 0  | 1  | 5       |
| 6         | 0      | 1  | 1  | 0  | 6       |
| 7         | 0      | 1  | 1  | 1  | 7       |
| 8         | 1      | 0  | 0  | 0  | 8       |
| 9         | 1      | 0  | 0  | 1  | 9       |
| 10        | 1      | 0  | 1  | 0  | 10      |
| 11        | 1      | 0  | 1  | 1  | 11      |
| 12        | 1      | 1  | 0  | 0  | 12      |
| 13        | 1      | 1  | 0  | 1  | 13      |
| 14        | 1      | 1  | 1  | 0  | 14      |
| 15        | 1      | 1  | 1  | 1  | 15      |

Work principle

  1. Clock is active, if FF output is always toggle, all outputs are 0
  2. Clock 1, FF1 is active Q1 = 1, FF1 - FF4 are not active yet, so Q2 - Q4 = 0
  3. Clock 2, FF1 is active Q1 = 0, FF2 is active Q2=1, FF3 and 4 are inactive so Q3 and 4 = 0
  4. Clock 3, FF1 is active Q1 = 1, FF2 - FF4 is inactive, then the condition of Q2 - Q4 is as before
  5. Clock 4, FF1 active Q1 = 0, FF2 active Q2 = 0, FF3 active, Q3 = 1, FF4 inactive, Q4 = 0
  6. Clock 5, FF1 is active Q1 = 1, FF2 is inactive, then Q2 - Q4 = 0
  7. Clock 6, FF1 is active Q1 = 0, FF2 is active Q2 = 1, FF3 and FF4 are inactive, so Q3 and Q4 are still in their previous state.
  8. Clock 7, FF1 is active Q1 = 1, FF2 - FF4 are inactive, so Q2 - Q4 are still in the previous condition
  9. Clock 8, FF1 active Q1 = 0, FF2 active Q2 = 0, FF3 active, Q3 = 0, FF4 active, Q4 = 1
  10. Clock 9, FF1 is active Q1 = 1, FF2 - FF4 are inactive, so Q2 - Q4 are still in the previous condition
  11. Clock 10, FF1 is active Q1 = 0, FF2 is active Q2 = 1, FF3 - FF4 are inactive, then Q3 and Q4 are still in their previous condition.
  12. Clock 11, FF1 is active Q1 = 1, FF2 - FF4 are inactive, then Q2 - Q4 = still in the previous condition
  13. Clock 12, FF1 is active Q1 = 0, FF2 is active Q2 = 0, FF3 is active, Q3 = 1, FF4 is inactive, Q4 is still in the previous state
  14. Clock 13, FF1 is active Q1 = 1, FF2 - FF4 are inactive, so Q2 - Q4 are still in the previous condition
  15. Clock 14, FF1 is active Q1 = 0, FF2 is active Q2 = 1, FF3 and FF4 are inactive, so Q3 and Q4 are still in their previous state.
  16. Clock 15, FF1 is active Q1 = 1, FF2 - FF4 is inactive, Q2 - Q4 is still in the previous state.

4. Initialize 7 Segment Common Anode


7 Segment Configuration

The display that is widely used in digital equipment is segment, because it is formed with 7 LEDs, it is called "seven segment", common anode is all anode pins combined into 1, while common cathode is the cathode leg combined into 1, in addition to pins a, b, c, d, e, f, g. also equipped with DP (Decimal Point).

5. Down Counter


Down Counter Schematic

Output Table

| Clock Ke- | Output |    |    |    | Desimal |
|-----------|--------|----|----|----|---------|
|           | Q4     | Q3 | Q2 | Q1 |         |
| 0         | 1      | 1  | 1  | 1  | 15      |
| 1         | 1      | 1  | 1  | 0  | 14      |
| 2         | 1      | 1  | 0  | 1  | 13      |
| 3         | 1      | 1  | 0  | 0  | 12      |
| 4         | 1      | 0  | 1  | 1  | 11      |
| 5         | 1      | 0  | 1  | 0  | 10      |
| 6         | 1      | 0  | 0  | 1  | 9       |
| 7         | 1      | 0  | 0  | 0  | 8       |
| 8         | 0      | 1  | 1  | 1  | 7       |
| 9         | 0      | 1  | 1  | 0  | 6       |
| 10        | 0      | 1  | 0  | 1  | 5       |
| 11        | 0      | 1  | 0  | 0  | 4       |
| 12        | 0      | 0  | 1  | 1  | 3       |
| 13        | 0      | 0  | 1  | 0  | 2       |
| 14        | 0      | 0  | 0  | 1  | 1       |
| 15        | 0      | 0  | 0  | 0  | 0       |

6. Counter With Module


Counter by Module

Output Table

| Clock Ke- | Output |    |    |    | Desimal |
|-----------|--------|----|----|----|---------|
|           | Q4     | Q3 | Q2 | Q1 |         |
| 0         | 0      | 0  | 0  | 0  | 0       |
| 1         | 0      | 0  | 0  | 1  | 1       |
| 2         | 0      | 0  | 1  | 0  | 2       |
| 3         | 0      | 0  | 1  | 1  | 3       |
| 4         | 0      | 1  | 0  | 0  | 4       |
| 5         | 0      | 1  | 0  | 1  | 5       |
| 6         | 0      | 1  | 1  | 0  | 6       |
| 7         | 0      | 1  | 1  | 1  | 7       |
| 8         | 1      | 0  | 0  | 0  | 8       |
| 9         | 1      | 0  | 0  | 1  | 9       |
| 10        | 1      | 0  | 1  | 0  | 10      |
| 11        | 1      | 0  | 1  | 1  | 11      |
| 12        | 0      | 0  | 0  | 0  | 0       |

7. Tone Decoder


Tone Decoder Circuit

8. Set Reset (RS) Flip-Flop

Truth Table

| S | R | Q  | Q^  | Ket   |
|---|---|----|-----|-------|
| 0 | 0 | Qn | Qn^ | *     |
| 0 | 1 | 0  | 1   | SET   |
| 1 | 0 | 1  | 0   | RESET |
| 1 | 1 | Qn | Qn^ | #     |

Information:

  • x = not allowed
  • # = same as previous condition, if (1-0) then (1-0)

The image above shows the circuit and symbols of the RS FLIP-FLOP and its truth table where changes in the input cause changes in the output if (s) is given logic (0) and (R) is given (1), then the output of gate (1) / Q = 1, so that the 2 inputs of gate 2 will be the same, namely logic (1) this will cause the output Q not or gate 2 will be (0) then fed back to gate (1) and the output of gate (1) will be (1) and so on and to change this condition, the inputs R and S must be given different inputs.

9. Clock Set Reset (RST) Flip-Flop


FF Reset Clock

Truth Table

| S | R | Q  | Q^  | Ket       |
|---|---|----|-----|-----------|
| 0 | 0 | Qn | Qn^ | Tetap     |
| 0 | 1 | 0  | 1   | RESET     |
| 1 | 0 | 1  | 0   | SET       |
| 1 | 1 | 1  | 1   | Terlarang |

A variation of the basic form of RS FF is that the block circuit has an additional input marked clock input. The working operation of this circuit is identical to RS FF but to operate it there must be a clock input. If the clock input is at logic zero, data from SR (input) will not be able to enter the circuit so that the output remains unchanged. RST FF can be triggered with logic 1/0 if the input data from S and R enter the FF when changing from 0 to 1:

So the circuit is called a "positive edge trigger" and if the opposite is from 1 to 0, then it is called a "negative edge trigger":

10. Logic Gate Simulation

11. Probe Checker

Probe Checker is an implementation of logic gates and is used as a tool to detect the presence of digital signals in an electronic circuit, where the maximum voltage that can be detected is 5 volts.


Probe Checker

Basic Theory of: 

  • ANDGATE = 7408
  • OR GATE = 7432
  • NOT GATE = 7404
  • NAND GATE = 7400
  • NOR GATE = 7402

How It Works 1


Floating condition = 1, no input, output = 0, LED OFF

How It Works 2


Floating condition or no input = 0, no output = 1, LED ON

12. Data (D) Flip-Flop


FF data is formed from RST FF

Work principle

When the data S = 1 and r = 0, then the data will be entered making Q = 1 and Q = 0 when there is an input clock that changes from 0 to 1 if the data is 0, then making the output Q = 0 and Q = 1.

| T                            | D | Q  | Q^  | Ket   |
|------------------------------|---|----|-----|-------|
| 1                            | 1 | 1  | 0   | Tetap |
| 1                            | 0 | 0  | 1   | RESET |
| 0                            | X | Qn | Qn^ | SET   |
| Keterangan : x = boleh 1 / 0 |   |    |     |       |

13. Toggle (T) Flip-Flop


DFF can form Toggle Flip-Flop

14. JK Flip Flop

Truth Table

| CLOCK  | J | K | Q  | Q^  |
|--------|---|---|----|-----|
| ENABLE | 0 | 0 | Qn | Qn^ |
|        | 0 | 1 | 0  | 1   |
|        | 1 | 0 | 1  | 0   |
|        | 1 | 1 | Qn | Qn^ |

The operating model of 3 FF is determined by the input J and K, for example we give J and K logic 1, then the FF will function as a Toggle FF, while if we give logic 0 to J and K, then the output will not change, to work normally, then Set and Reset are given logic 1, if clear/reset is given 0, then the JK FF output will Reset = Q = 0 and Q not = 1 in the same way Reset input can be used for Set, namely Q = 1 and Q not = 0.

15. Shift Register (Ring Counter)

Work principle

  1. Input data = 1 on FF, then L1 to L4 are OFF
  2. Activate the clock, then the data will be output by FF and L1 ON while L2 - L4 OFF
  3. Enter data 0 on FF1 and activate the clock, then L1 is OFF, L2 is ON, L3 and L4 are OFF
  4. Clock active, L1 and L2 OFF, L3 ON, L4 OFF
  5. Clock is on, L1, L2 and L3 are OFF, L4 is ON
  6. Clock is on, L1 - L4 is OFF.


Output Ring Counter

RING COUNTER (2)

Work principle

  1. Input data = 1 on FF1, then L1 - L4 is OFF
  2. Clock 1 active, L1 ON, L1-L4 OFF
  3. S1 OFF, S2 ON, clock 2 ON, L2 ON, L1, L3 AND L4 OFF
  4. Clock 3 ON, L3 ON, L1, L2 AND L4 OFF
  5. Clock 4 ON, L4 ON, L1-L3 OFF
  6. Clock 5 ON, Return to clock 1 (same situation as no.2)
  7. Clock 6 ON, back to clock 2 (same situation as no.3)
  8. Clock 7 ON, back to clock 3 (same situation as no.4)
  9. Clock 8 ON, back to clock 4 (same situation as no.5)
  10. This pattern will continue, meanwhile to display a ring counter, it is arranged to form a circle. then it is called "Ring Counter".


Ring Counter Configuration

Microcontroller Software

Subject:

  1. ASSEMBLY RESOURCE PROGRAM
  2. LABEL
  3. MNEMONICS
  4. OPERAND
  5. COMMENT
  6. OBJECT PROGRAM
  7. ASSEMBLY LISTING


Microcontroller Programming Basics

1. Assembly Source Program

Assembly source program is a set of command lines saved with the extension *.ASM. This program is written using text editor software such as Notepad or DOS Editor.


Example of writing assembly instructions

2. Label


Assembly Program Example

Label writing requirements:

  • Must start with a letter
  • There can't be any identical labels
  • Maximum 16 characters
  • There should be no spaces

3. Mnemonics

Mnemonic or called operation code or OPCode (Operation Code) is the command code that will be executed by the assembly program that has been created and downloaded to the microcontroller. This Operation Code is a command or instruction that already exists (embedded) in the microcontroller library, besides that it also depends on the type of microcontroller.

For example, several commands for the same function, but written differently:

  • For MCS51 family move : MOVX, MOV, ADD, etc.
  • Assembler directives: ORG, EQU, DB

4. Operand

Operands are the complement of mnemonics, the number of operands required by a mnemonic is not always the same, a mnemonic can have three, two, one or even no operands as seen in the following example:


Examples of Operand Usage

5. Comments

The comment section is not absolute in a program, but this section is often needed to explain the work process or certain notes in the program section. Even program makers often need to remember the course of their designed program, and it always starts with ";"


Example comments

6. Object Program

The object program is the main program of the assembler / assembly program compilation process, which is only recognized by the microprocessor / microcontroller. The object program can be either hex code ( . HEX) or binary ( . BIN).


Assembler / Compilation Process

7. Assembly Listing

Assembly listing is the result of the assembly process in the form of a combination of object programs, assembly source programs and their addresses. Assembly listing is stored in a file with the extension (*.LST).


Assembly listing

Sequential Circuit Design

A sequential circuit is a circuit whose output depends not only on the current state, but also on the previous state of the input. In this chapter we learn the method of designing memory circuits, statements used to create sequential circuits, examples of circuits along with their implementation and simulation using the VHDL simulator.

1. Statement Process 

To create a sequential circuit, we need to execute statements sequentially as in general programming languages ​​(C, C++, Paskal, etc.). In a VHDL architecture, all statements are executed simultaneously (concurrent). But there is a special statement, namely PROCESS, where all VHDL statements in this statement will be executed sequentially.

Structure 

The process statement structure can be seen below.

label : PROCESS(sensitivity_list)
BEGIN
Statement..1
Statement..2
Statement..3 END

As seen in Figure II.1 statement_1, statement_2, statement_3 will be processed sequentially. After statement_3 is executed, the process will return to executing statement_1.

Sensitivity List 

Sensitivity List is a list of one or more signals, which if the value of one of them changes, then the statement in the process will be executed. An easy example of using a sensitivity list is the use of a clock in a combinational circuit. A sequential circuit is always executed based on the changing value of the clock signal. Thus the use of a sensitivity list can be made as follows:

Clock signal as sensitivity list of sequential circuit

PROCESS(clock)
BEGIN
Statement..1
Statement..2
Statement..3 END

From the example above, the statement will be executed if the clock value changes from 1 to 0 or from 0 to 1.

2. Sequential Statements

In this section, we will discuss several VHDL statements that are used sequentially in the PROCESS statement.

IF Statement 

The structure of the IF statement can be seen below.

Process Statement Structure. Note: statements inside the "[ ]" symbols are optional.

IF condition THEN
 Statement_1... [ELSIF condition THEN  statement_1...]
 [ELSE  statement_1...]
END IF;

Just like most programming languages, statements in IF will only be executed if the condition of the IF or ELSIF is met. The condition must be made in the form of a BOOLEAN expression, which produces a TRUE or FALSE condition. If it is not met, then the condition in ELSE will be executed.

Some examples of conditions for IF statements are as follows:

Creating a condition statement from IF

Example 1:

IF reset ='1' THEN
data <= "00000000";
ELSIF increment='1' THEN
data <= data + "00000001";
ELSE
data <= data;
END IF;

Example 2:

IF en ='1' AND counter<"1111" THEN
data <= data + "00000001";
ELSE
data <= "00000000";
END IF;

In example 1, it can be seen that if the reset signal is '1', then the data signal will be given the value "00000000". In other conditions, namely when reset = '0' and signal increment = '1', then the value of the data signal will be increased by one. And if both conditions are not met, namely reset = '0' and increment = '0', then the value of the data signal will remain "00000000".

Example 2 shows almost the same condition, only showing the use of the < sign and the "AND" statement. We can place various arithmetic operations in the condition, as long as the result obtained is TRUE/'1' or FALSE/'0'.

Although the ELSE condition is optional, to ensure that the circuit synthesized from the VHDL description produces a circuit as expected, try to always create statements in the ELSE condition.

CASE Statement 

The structure of the CASE statement can be seen below.

CASE Statement Structure. Note: statements inside the "[ ]" symbols are optional.

CASE expression IS
 Statement_1...
WHEN pilihan(|pilihan) =>  statement_1...; WHEN pilihan(|pilihan) =>  statement_1...;
...
WHEN OTHERS =>  statement_1...;

END CASE;

The CASE statement is used to assign a signal that has several alternative conditions. The signal that becomes the condition is placed as an expression of the CASE statement. Each condition is represented by a WHEN statement. If the expression satisfies one of the choices, then the statements that follow the WHEN choice=> will be executed sequentially. 

Examples of use are as follows:

CASE mode IS
WHEN add =>      acc <= a+b;
WHEN sub =>      acc <= a-b; WHEN OTHERS      acc <= a;
END CASE;

In the above example, mode is an expression whose value is checked, thus determining what operation is performed to produce a value for acc.

3. Simple Sequential Circuit Design

This section will explain how to create VHDL descriptions for circuits that are widely used in sequential circuits.

D Flip-Flop Design

D Flip-flop is a memory element that can store previous input data. D Flip will sample input data when the clock value changes from 0 to 1 (rising edge). Thus, the clock is used as a sensitivity list of the circuit as seen in Figure II.5. To distinguish when the flip-flop samples input data, then, we need to use the IF statement as in the example.

DFF circuit description

dff: PROCESS(clk)
BEGIN
IF reset =’1’ THEN
data <= ‘0’;
ELSIF (en=’1’) THEN
IF clk=’1’ AND clk’EVENT THEN
data <= data_in;
END IF;
ELSE
data <= data;
END IF;

The en signal is an enable signal which functions to activate the flip-flop. All transitions can only occur if en='1'.

The clk'EVENT statement is to limit the process execution to occur at the time of the clock value transition. If this statement is combined with the clk='1' statement, then the execution will occur at the rising edge. Conversely, if clk='0', then the process will be executed at the falling edge.

The circuit above can be simulated using the dff.vhd and dff_tb.vhd circuits. The simulation results can be shown with the timing diagram in Figure II.6. In the figure, the data is sampled at the rising edge of the clock.

The D Flip-flop above is a synchronous D flip-flop, where the reset condition can only be achieved if there is a clock (rising edge). To obtain a D flip-flop with an asynchronous reset (can occur without changes in the clock), then we must include the reset signal in the sensitivity list, so that the VHDL code becomes:

Description of DFF circuit with asynchronous reset

dff: PROCESS(reset, clk) 
BEGIN 
IF reset =’1’ THEN  data  <= ‘0’; 
ELSIF (en=’1’) THEN

4Bits Counter Design 

Counter circuit is a circuit that is widely used in combinational circuits. 8 bits counter can be implemented as below.

Description of VHDL counter 8 bits

library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-----------------------------------------------------
entity counter4 is
port( en : in std_logic;
clock: in std_logic;
reset: in std_logic;
sc_in: in std_logic;
sc_en: in std_logic;
sc_out: out std_logic;
cout : out std_logic_vector(3 downto 0)
);
end counter4;
-----------------------------------------------------
architecture behave of counter4 is
signal counter : std_logic_vector(3 downto 0);
begin
process(clock)
begin
if clock'event and clock = '1' then
if en = '0' then
if (reset = '1' or counter = "1111") then
counter <= (others => '0');
else
counter <= counter + "0001";
end if;
end if;
end if;
end process;
cout <= counter;
end behave;

As seen above, the count register value can be increased by giving a value of '1' to the inc signal. The count register value becomes "00000000" when it is reset or the counter reaches its maximum value of "11111111".

The circuit above can be simulated using the count8.vhd and count8_tb.vhd circuits. The simulation results can be shown with the timing diagram in Figure II.6. In the figure, the data is sampled at the rising edge of the clock.

State Machine Design

An example of a simple state machine is the red light state machine as shown in the figure below.


Figure II.9 State and block diagram of Traffic light controller

As can be seen in the state diagram, in the initial condition the system is under research and is in an idle state. If en='1', then the state will change to idle?green, green?yellow, yellow?red, red?green. Except if en='0' in each condition then the state will move to idle. 

From this state machine we can design the VHDL description as follows: 

  • Determine the number of states. From the diagram we can see that the system consists of 4 states. Thus we can represent the states with a 2-bit register, in this case ctrl_state. In VHDL code: signal ctrl_state: std_logic_vector(1 downto 0);
  • Determining the Sensitivity list. In this case, the state change occurs at the rising edge of the clock, so the sensitivity list can be determined to be the clock.
  • Conditions for state change. From the state diagram it can be seen that the state changes due to the signal function en.

From these stages we can create a VHDL description of the state machine as follows:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity trafic is
port(
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
state : out std_logic_vector (1 downto 0)
);
end trafic;
architecture trafic_bhv of trafic is
signal ctrl_state : std_logic_vector(1 downto 0);
begin
process(clk)
begin
if (clk = '1' and clk'event) then
if (rst = '1') then
ctrl_state <= "00";
elsif (en = '1') then
case ctrl_state is
when "00" =>
ctrl_state <= "01";
when "01" =>
ctrl_state <= "10";
when "10" =>
ctrl_state <= "11";
when "11" =>
ctrl_state <= "00";
when others =>
ctrl_state <= "00";
end case;
else
ctrl_state <= "00";
end if;
end if;
end process;
state <= ctrl_state;
end trafic_bhv;

Another way to describe the traffic controller is by using the IF THEN statement. The results of the design simulation are as follows:

Design of 8Bits Parallel to Serial Converter 

In this section, the design stages of 8 bits parallel to serial converter will be explained. This system functions to convert 8 bits data that comes every 8 clocks. Serial data will be output through the serial port every clock. The block diagram of this system can be seen in the following image:

This system can be divided into registers and controllers. Registers function to receive parallel 8 bits of data when the registers are in parallel mode, and perform serial shifts when the register is in serial mode.

In addition to the register, the system has a controller, which functions to determine when the register receives parallel data and when to shift data serially. The state machine of the controller block can be seen in the following figure:

The VHDL code of this system is as follows:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity prl2srl is
port(
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
prl : in std_logic_vector (7 downto 0);
srl : out std_logic
);
end prl2srl;
architecture prl2srl_bhv of prl2srl is
signal ctrl_state : std_logic;
signal srl_cnt : std_logic_vector(2 downto 0);
signal buff : std_logic_vector(7 downto 0);
begin
ctrl : process(clk)
begin
if (clk = '1' and clk'event) then
if (rst = '1') then
ctrl_state <= '0';
elsif (en = '1') then
case ctrl_state is
when '0' =>
ctrl_state <= '1';
when '1' =>
if (srl_cnt = "111") then
ctrl_state <= '0';
else
ctrl_state <= ctrl_state;
end if;
when others =>
ctrl_state <= ctrl_state;
end case;
else
ctrl_state <= '0';
end if;
end if;
end process;
cnt : process(clk)
begin
if (clk = '1' and clk'event) then
if (rst = '1' or ctrl_state = '0') then
srl_cnt <= "000";
else
srl_cnt <= srl_cnt+"001";
end if;
end if;
end process;
Pbuff : process(clk)
begin
if (clk = '1' and clk'event) then
if (rst = '1') then
buff <= "00000000";
elsif (ctrl_state = '0') then
buff <= prl;
elsif (ctrl_state = '1') then
buff <= buff(6 downto 0) & '0';
end if;
end if;
end process;
srl <= buff(7);
end prl2srl_bhv;

The simulation results of this system can be seen in the following image:

Author: Dr. Trio Adiono Date: Wednesday, December 07, 2005

Understanding Flip-Flop Sequential Circuits

Previously we have learned about combinational logic units whose output only depends on the current input or in other words the output is a function of the input only. Sequential logic units or often referred to as finite state machines (FSM), their output depends on the previous input and output. FSM is distinguished from CLU because in addition to producing output it also produces a state. This is important for the implementation of memory circuits and also control units on computers.

The classic model of FSM is shown in Figure 4.1. The CLU section has input from the i0 - ik path originating from outside the FSM and also state input s0 - sn originating from within the FSM itself. The CLU produces output bits f0 - fm and the latest state bit. With the presence of a delay element, the current state persists until there is a synchronization signal that causes the value of Di to replace the value of si as the new state bit, because it is taken from Qi.

There are several types of sequential digital logic, including:

  1. SR Flip Flop
  2. SR Ticking Flip-Flop
  3. D Flip-flop and master-slave configuration
  4. JK Flip Flop
  5. T Flip Flop

One of the most useful logic circuits is the sequential logic circuit that is interconnected for storage, timing, calculation and sequencing. The basic form of a sequential logic circuit is a flip-flop circuit assembled from NAND and AND logic gates.

Another name for flip-flop is bistable multivibrator, where the output is low voltage (0) or high (1). This output will remain low or remain high as long as there is no input that changes the state. The circuit in question must be driven (controlled) by one input called a trigger. The state will change again if there is another trigger input. There are 3 types of multivibrators, namely: astable, monostable, and bistable. The image below only discusses bistable multivibrators (flip-flops).

Based on the storage method, flip-flops can be classified as:

  1. RS Flip Flop
  2. JK Flip Flop
  3. D Flip Flop
  4. T Flip Flop

1. RS Flip-Flop

This flip-flop has 2 inputs and 2 outputs. The inputs are S=Set and R=Reset, while the outputs are Q and Q^ (read Q not). It acts as 1 bit of memory with the output Q as the value of that bit. S=1, R=1 is not allowed (cannot be set simultaneously) because it will produce inconsistent output. The RS Flip-Flop can be formed from a combination of two NAND gates or a combination of two NOR gates. See figure 31 and figure 32.


Fig.31 RS Flip-Flop Schematic


Fig.32 RS Flip-Flop Simulation

2. D Flip-Flop

It is a modification of the RS flip-flop with the addition of an inverting gate on the R input, so that the R input is the complement of the S input. When D = 0 the flip-flop is reset (Q = 0), while when D = 1, the flip-flop is set (Q = 1). You can see it in figures 33 and 34.


Fig.33 D Flip-Flop Schematic


Fig.34 D Flip-Flop Simulation

3. JK Flip Flop

This flip-flop has 2 inputs and 2 outputs, where one of the outputs (PRE) / (Y) functions as a complement. JK flip-flop can be formed from a combination of 4 NAND gates, this flip-flop does not have a forbidden state like the RS flip-flop. See figures 35 and 36.


Fig.35 JK flip-flop schematic


Fig.36 JK flip-flop simulation

4. T Flip-Flop

It is a modification of the JK flip-flop, by combining two inputs J and K so that the output (y) will change according to changes in the clock. See figures 37 and 38.


Fig.37 Schematic of T flip-flop


Fig.38 T flip-flop simulation

Understanding D Flip-Flop & Master-Slave Configuration

The disadvantage of the SR flip-flop is that to store a 1 or 0, we must load a 1 on S or R. An alternative configuration for storing a 1 or 0 is to use a D flip-flop as shown in Figure 4.8. The D flip-flop is composed of a flip-flop with an inverting device between the S and R inputs. Thus, when the clock moves up, the value on the D line will be stored.


Figure 4.8 Flip-flop D. Symbol C indicates clock or clock.

Flip-flops are commonly used in circuits that have feedback from the output back to the input path through another circuit. This sometimes causes the state of the flip-flop to change more than once in a single clock cycle. To ensure that only 1 state change occurs in a single cycle, we intercept the feedback loop by forming a master-slave flip-flop as in Figure 4.9.


Figure 4.9 Master-slave flip-flop

The master-slave flip-flop consists of two flip-flops in series with the clock for the second flip-flop inverted. The master flip-flop changes state when the clock is high, but the slave flip-flop does not change state until the clock is low. Thus, a rising and falling clock is required to move the contents of the D line on the master flip-flop to the Qs output on the slave flip-flop. The triangle symbol on the master-slave flip-flop indicates that the state change occurs only when the clock changes state up (from 0 to 1) or down (from 1 to 0). For a configuration like Figure 4.9, the state change occurs when the clock goes down (from 1 to 0).

Level-triggered flip-flops change state continuously as long as the clock is high (or low depending on the flip-flop design). Edge-triggered flip-flops change state only when the clock changes from high-to-low or from low-to-high. Some books do not put the triangle symbol on the clock input. Other methods are used to distinguish between level-triggered and edge-triggered flip-flops. The use of the triangle symbol makes the type of flip-flop clear.

Understanding JK Flip-Flop & T Flip-Flop

In addition to the SR and D flip-flops, the JK flip-flop is also a fairly well-known flip-flop. The JK flip-flop behaves similarly to the SR flip-flop except that this flip-flop will have an output of Q=1 for J=1 and K=0. When J=0 and K=1, the output is Q=0. If J and K are 1, the output value will be the opposite of the previous output value. However, for J and K both being 0, the output will remain the same. The logic diagrams and symbols for the JK and T flip-flops are shown in Figures 4.10 and 4.11


Figure 4.10 JK flip-flop and its symbol

The problem when operating in alternating mode is that if J and K are both high and the clock is also high, the flip-flop can alternate values ​​more than once until the clock goes low.


Figure 4.11 T flip-flop and its symbol

This situation is one of the reasons for using the master-slave configuration. The schematic diagram for a master-slave JK flip-flop is shown in Figure 4.12.


Figure 4.12 JK master-slave flip-flop and its symbol

Understanding SR Flip-Flop

A flip-flop is a logic gate arrangement that maintains a stable output even when the input is no longer active. The output of a flip-flop is determined by the value of the input and also the previous output value, so a combinational logic unit is not sufficient to handle this. Flip-flops can be used to store single bits of information, and act as a building block of computer memory.


Classical model of FSM

If both inputs of a two-input NOR gate are 1, then the output will be 0, otherwise the output will be 1. As discussed in the previous chapter, the time required to produce the output from the input of a logic gate is not instantaneous but is equal to the propagation time through the logic gate. This delay is sometimes shown as a series of delays for analysis purposes as shown in the figure below. This delay is not normally shown but is still present.


NOR gate with delay circuit

The propagation time through a NOR gate affects the operation of a flip-flop. Consider the set-reset (SR) flip-flop in Figure 4.3, which contains crossed NOR gates. If we put a 1 on S, Q^ will be 0 after a delay of Δt , which causes Q to be 1 (assuming R to be 0) after a delay of 2Δt . The result is that for a short period of time Δt both Q and Q^ are 0, which is logically unacceptable, but this condition can be corrected by the master-slave configuration that we will discuss later. If S is then put to 0, Q remains the same until R becomes 1. The SR flip-flop can thus store a single-bit value and can act as the most basic memory element.


Figure 4.3: SR flip-flop with NOR

There are many ways to construct an SR flip-flop. Using crossed NOR gates for an SR flip-flop is just one way. Two crossed NAND gates can also produce an SR flip-flop, with S = R = 1 leaving the output unchanged. Using DeMorgan's theorem we can convert the NOR gates in an SR flip-flop into AND gates as shown in Figure 4.4. By shifting the bubbles, the AND gates can be converted into NAND gates. Shifting the bubbles on S and R causes the labels of S and R to be swapped.


Figure 4.4: SR flip-flop with NAND

SR Ticking Flip-Flop

It is important to note that the input to the SR flip-flop can come from the output of another circuit, in the form of a cascaded logic circuit. This is common in conventional logic circuits. The problem is that the transitions can occur at undesired times.

Consider the circuit in Figure 4.5. If signals A, B, and C all change from 0 to 1, then signal C will reach the XOR gate before A and B exit the AND gate. As a result, the value of S will be 1, although briefly, until the output of the AND gate is stable and XORed with C. If the value of 1 in S persists long enough, it will cause the value stored in the flip-flop to change.


Figure 4.5 A circuit containing a hazard

If the final state of the flip-flop is sensitive to the arrival of a signal, it can cause a glitch, which is actually an unwanted state or output. A circuit that can produce a glitch is called a circuit that contains a hazard.

To synchronize control of a circuit that depends on conditions (for example flip-flops), a clock is used that will activate the circuit at certain intervals simultaneously. The clock circuit produces alternating 1 and 0 signals continuously with a fixed time period to form a square wave as in Figure 4.6. The time required for the clock to rise, fall and then start rising again is called the cycle time or period. The square wave shown in the figure is an ideal clock waveform. In reality, the waveform is not square but rounded because it takes time to become high and low, it does not happen instantly.


Figure 4.6 Beat in the form of a square wave

The clock rate is the inverse of the cycle time. For a cycle time of 25 ns/cycle, the speed is 1/25 cycle/ns, which is equal to 40,000,000 cycles per second or 40 MHz.

We can use a clock signal to eliminate the hazard by making the SR flip-flop tick, as shown in Figure 4.7. The symbol CLK stands for clock. Now S and R cannot change state until the clock is high. So S and R are first made steady at the low clock, then the clock goes high and the stable value is stored in the flip-flop.


Figure 4.7 SR flip-flop ticking

LED Display Microcontroller Experiment

OBJECTIVE:

  • Students understand the microcontroller circuit to turn the LED on and off.
  • Students can understand assembly programs to turn LEDs on and off.
  • Students understand some basic assembly instructions, MOV, Setb, Clr, RL and RR.
  • Students understand how to create delay time instructions


Figure 1.1 LED Display Circuit

Look at the picture 1.1. Eight LEDs are connected to port 0, which functions as output. In this configuration, the LED will light up when given a LOW logic '0' through port 0, and the LED will go out when given a HIGH logic '1' through port 0. In order for this LED Display to be active, the EN LED jumper must be connected short.

Experiment 1.1.MOV Instruction

In experiment 1.1, the LED will be turned on or off by sending certain data to port 0. To perform this experiment, do the following steps:

  1. Connect the jumper on LED_EN, to activate 8 LEDs.
  2. Connect the Microcontroller Trainer module to the +5V power supply.
  3. Connect the Microcontroller Trainer module to the programmer circuit 
  4. Open the M-IDE Studio for MCS-51 program, as a program editor and compiler.
  5. Type the following program 🙁download file prog11a.asm )
    Org 0h
Start: Mov P0,#00000000b; Menghidupkan 8 buah LED
End
  6. Save the program you typed and name it: prog11a.asm</ li>
  7. In the MIDE program, select Build /F9 or to compile the program from *.asm to *.hex.
  8. Program the microcontroller using the ISP Software Program (See Instructions for Use)
  9. Make observations on the LED
  10. Replace the data above with the data in the following table and record which LEDs are off.

Experiment 1.2. Creating a Time Delay Subroutine

In this experiment, 8 LEDs will blink continuously. To do this experiment, do the following steps:

  1. Connect the Microcontroller Trainer module to the +5V power supply.
  2. Connect the Microcontroller Trainer module to the programmer circuit 
  3. Open the M-IDE Studio for MCS-51 program, as a program editor and compiler.
  4. Type the following program:  download file prog12a.asm
Org 0h
 Start: Mov P0,#11111111b; Kirim data biner 11111111 ke P0
           Call Delay ; Memanggil waktu tunda
           Mov P0,#00000000b; Kirim data biner 00000000 ke P0
           Call Delay ; Memanggil waktu tunda
           Sjmp start
           ;
Delay: mov R1,#255
 Del1: mov R2,#255
 Del2: djnz R2,del2
           djnz R1,del1
           ret

           end
  1. Save the program you typed and name it: prog12a.asm
  2. In the MIDE program, select Build /F9 or to compile the program from *.asm to *.hex.
  3. Program the microcontroller using the ISP Software Program (See Instructions for Use)
  4. Make observations on the LED
  5. Replace the data to blink one LED, two LEDs and so on, according to the following table.

Experiment 1.3. Setb and Clr Instructions

In this experiment, one or more LEDs can be turned on or off with the setb and clr commands. To do this experiment, do the following steps:

  1. Connect the Microcontroller Trainer module to the +5V power supply.
  2. Connect the Microcontroller Trainer module to the programmer circuit 
  3. Open the M-IDE Studio for MCS-51 program, as a program editor and compiler.
  4. Type the following program 🙁download file prog13a.asm )
    Org 0h
Start: Clr P0.0 ; Mengirimkan logika '0' ke P0.0
           Sjmp start ; jump ke start
end
  5. Save the program you typed and name it: prog13a.asm
  6. In the MIDE program, select Build /F9 or to compile the program from *.asm to *.hex.
  7. Program the microcontroller using the ISP Software Program (See Instructions for Use)
  8. Make observations on the LED
  9. Change the data to turn on the other LEDs: LED 2, LED 3, LED 4, LED 5, LED 6, LED 7 and LED 8.
  10. Do the following experiment to blink LED 1, by typing the following program.
    Org 0h
Start: Clr P0.0 ; Kirim logika '0' ke P0.0
           Clr P0.1 ; Kirim logika '0' ke P0.1
           Clr P0.2 ; Kirim logika '0' ke P0.2
           Clr P0.3 ; Kirim logika '0' ke P0.3
           Clr P0.4 ; Kirim logika '0' ke P0.4
           Clr P0.5 ; Kirim logika '0' ke P0.5
           Clr P0.6 ; Kirim logika '0' ke P0.6
           Clr P0.7 ; Kirim logika '0' ke P0.7
           Call Delay ; Memanggil waktu tunda
           Setb P0.0 ; Kirim logika '1' ke P0.0
           Setb P0.1 ; Kirim logika '1' ke P0.1
           Setb P0.2 ; Kirim logika '1' ke P0.2
           Setb P0.3 ; Kirim logika '1' ke P0.3
           Setb P0.4 ; Kirim logika '1' ke P0.4
           Setb P0.5 ; Kirim logika '1' ke P0.5
           Setb P0.6 ; Kirim logika '1' ke P0.6
           Setb P0.7 ; Kirim logika '1' ke P0.7
           Sjmp start ; lompat ke start
           ;
Delay: mov R1,#255
Del1: mov R2,#255
Del2: djnz R2,del2
           djnz R1,del1
           ret
           end

Plan a program to blink two LEDs, three LEDs and so on with the Setb and Clr instructions.

Experiment 1.4. RL/RR Instructions (Rotate Left and Right)

In this experiment, an LED will run from left to right and vice versa, this program utilizes the RL and RR instructions. To do this experiment, do the following steps:

  1. Connect the Microcontroller Trainer module to the +5V power supply.
  2. Connect the Microcontroller Trainer module to the programmer circuit 
  3. Open the M-IDE Studio for MCS-51 program, as a program editor and compiler.
  4. Type the following program 🙁download file prog14a.asm )
    Org 0H
Start: Mov A,#11111110b
           Mov R0,#7
           Kiri: Mov P2,A
           Call Delay
           RL A
           DEC R0
           CJNE R0,#0,Kiri
           Mov R0,#7
Kanan: Mov P2,A
           Call Delay
           RR A
           DEC R0
           CJNE R0,#0,Kanan
           Sjmp Start
           ;
Delay: mov R1,#255
Del1: mov R2,#255
Del2: djnz R2,del2
           djnz R1,del1
           ret
           end
  5. Save the program you typed and name it: prog14a.asm
  6. In the MIDE program, select Build /F9 or to compile the program from *.asm to *.hex.
  7. Program the microcontroller using the ISP Software Program (See Instructions for Use)
  8. Make observations on the LED
  9. Make changes to the program to run two LEDs left and right, three LEDs left and right, and so on.

Post a Comment

Previous Next

نموذج الاتصال