The output of the FSM circuit we have discussed so far is determined by the current state and the inputs. The state is maintained by a falling edge-triggered flip-flop, so state changes occur only during the falling edge of the clock. Any changes to the inputs have no effect on the state during the low clock. The inputs directly produce the outputs without passing through the flip-flops. Thus a change in the inputs can result in a change in the output, regardless of whether the clock is low or high. In Figure 4.25, a change in either input x1 or x0 can result in a change in the output z2z1z0 regardless of the clock. This type of FSM is called the Mealy FSM model.
Figure 4.25 Sales machine (a) circuit, (b) truth table (c) PLA realization
In the Mealy model, the output changes as soon as the input changes, so there is no delay caused by the clock. In the Moore FSM model, the output is integrated at the state bit, so the output changes at the clock pulse after the input changes. Both models are used by circuit designers and in this section we will discuss their differences by giving examples.
An example of a Moore FSM is the 2-bit binary counter shown in Figure 4.26. This machine counts from 0 to 3 and repeats from 0 again, similar to a modulo-4 counter. It only counts if x = 1, otherwise it stays in the current state. Note that the output is integrated into the state variable, so there is no direct path between the input and output that does not pass through the flip-flops.
The Mealy model is considered more powerful than the Moore model because a single pulse can cause a change in the output of one machine. This change in output can change the output of another machine, if it is connected to the input of the other machine, and so on. In the Moore model, changes are always synchronous with the pulse, so that successive changes between machines cannot occur. A change in the output of one machine has little effect on the next machine in the Moore model. Therefore, error analysis and tracking can be traced part by part more easily. In practice, both models are used.
Figure 4.26 Moore FSM of a 2-bit binary counter