IC Timer (ICT)

There are a large number of monolithic timer circuits available on the market today, but perhaps the best known are the 555, 556 and ZN 1034 E. Timing circuits are circuits that will provide a change in state of the output after a predetermined time interval.

This is, of course, the motion of a monostable multivibrator. Discrete circuits can be easily designed to provide time delays (from a few microseconds to several seconds), but usually very long delays require mechanical devices. The 555 timer IC, first available in 1972, allows for fairly accurate delays or oscillations from microseconds to several minutes, while the ZN 1034 E can be set to provide delays of up to several months.

The basic operation of the 555 can be easily understood by looking at Figure 6.112. For monostable operation, the external timing components RA and C are connected as shown in the figure. Without any driving pulse applied, the Q output of the flip-flop is high, forcing the discharge transistor on and keeping the output low.

The three resistors in Rl, R2 and R3 of 5 k ohms form a voltage divider chain so that a voltage of 2/3 Vcc arises at the inverting input of comparator 1 and a voltage of 1/3 Vcc at the non-inverting input of comparator 2. This driver input is connected to Vcc through an external resistor, so that the input of comparator 2 becomes low. The outputs of the two comparators control the state of the inner flip-flop. Without the application of a driver pulse, the output Q will be high and this will force the inner drain transistor to conduct.

Pin 7 will be at nearly 0 volts, and capacitor C will be prevented from charging. At the same time, its output will be low. When a negative drive pulse is applied, the output of comparator 2 will momentarily go high and set the flip-flop. The output Q will go low, the drain transistor will be turned off and its output will be switched high to Vcc. The outer timing capacitor C can now be charged through RA, so the voltage across it will rise exponentially to Vcc. When this voltage reaches 2/3 Vcc, the output of comparator 1 will go high and reset the inner flip-flop. The drain transistor will be connected and quickly discharge the timing capacitor, and at that moment the output will be switched to zero.

Figure 6.112: 555 Timer

Figure 6.112: Timer 555 output signal

The output pulse width tpw is equal to the time required for the external capacitor to charge from zero to 2/3 Vcc, tpw = 1.1 CRA.

The RA value can range from 1K ohm to (1.3 Vcc) M ohm. In other words, if a supply voltage of 10 V is used, the minimum RA value is 1 K ohm or a maximum of 13 M ohm. In practice, intermediate values ​​between 50 K ohm. and 1 M ohm are used, since these values ​​tend to give the best results. The 555 output switches between nearly zero (0.4 V) and about 1 volt below Vcc with a rise and fall time of 100 nseconds. The load can be connected from the output to ground or from the output to Vcc. The first connection is known as the current source mode and the second is known as the current sink. In both cases, a load current of up to 200 mA can be accommodated.

Two other input pins are also provided. Pin 4, the reset terminal, can be used to interrupt the timing and reset the output by applying a negative pulse. Pin 5, called control, can be used to modify the timing or modulate the delay time.

The voltage applied to pin 5 can disturb the dc level formed by the internal resistors. In normal timing applications when no modulation is required, pin 5 is usually taken to ground through a 0.01 VF capacitor. This prevents the pickup of noise that can affect the timing.

One of the important things about the 555 is that the time delay is relatively independent of changes in the supply voltage. This is due to the three internal resistors that set the ratio of the threshold level to the drive level at 2/3 Vcc and 1/3 Vcc. The change in time delay with respect to the supply voltage is 0.1 per volt.

In addition, the temperature stability of the microcircuit reaches its best value at 50 ppm per °C. Thus, the accuracy and stability of the time delay depend greatly on the quality of the external timing components RA and C. Electrolytic capacitors may have to be used for long-term delays, but the leakage current must be sufficiently low. Also, since the tolerance of electrolytic capacitors is quite large (-20% + 50%), part of the timing resistor may have to be a preset to allow the delay to be set sufficiently accurately.

An example of a 555 used as a simple 10-second timer is shown in Figure 6.113.

Figure 6.113: 10 Second Timer Using 555

Pressing the start button makes pin.2, the input trigger to 0 V. The output will be high and the LED will be on. Then C1 will be charged from 0 V until it reaches +Vcc. After 10 seconds, the voltage passing through C1 reaches 6 V (2/3 Vcc) and the 555 will be reset, its output will return to a low state.

The case:

The circuit fails to function with the symptom that the output always remains low. The solution is: a list of possible errors that may give this symptom is:

1. The power supply circuit to the IC is open.
2. Failure of the trigger circuit, namely the opening of the circuit switch contact or the opening of the circuit connection to pin 2 of the IC.
3. Failure in the IC 555 itself.
4. The circuit from pin 3 to the load is open.

If C1, the timing capacitor or its connections are open circuited, the time delay will be very short, but pressing the start switch will cause the output to go high, and this output will remain high as long as the start switch remains in that position. The solution is: To determine the location of the fault, the following inspection steps need to be carried out:

1. Check the power supply voltage using a voltmeter on the IC between pin 8 and pin 1.
2. Investigate the driver circuit. Pressing the start switch will cause pin 2 to drop from a positive value to 0 V. Because the driver of the 555 is very sensitive, a meter to pin 2 can cause the timer to turn on. This alone can be an indication that something is wrong with the start switch circuit and that the fault does not lie with the IC.
3. Check the output between pin 3 and pin 1 of the IC.
4. Check that pin 4, reset, is positive (Vcc) and that pin 5 is at 2/3 Vcc.

A fault such as R1 which is an open circuit will result in the output, once triggered will remain high. This is because Cl no longer has a charging path to Vcc. With this fault, the circuit will be reset by pressing S2. Similar symptoms will occur if the pcb path, or wiring from C1 to pins 6 and 7 becomes open, except that the voltage across C1 will rise positively. It should be noted that if voltage measurements are made across C1 or at pins 6 and 7, a high impedance meter must be used.

Some other linear ICs that have been discussed in the introduction such as regulators and analog-to-digital converters will be discussed in other chapters. One important consideration is the PLL (Phase Locked Loop). Basically this PLL (Figure 6.114) is a feedback system consisting of a phase detector, a low pass filter and a voltage controlled oscillator (VCO).

This VCO is an oscillator whose frequency will vary from its free running value when a dc voltage is applied. Analysis of PLL will not be done in this book. Without the application of an input signal, the output voltage will be zero and the VCO will operate freely at a frequency that has been set by the external component R1C1.

If an input signal of frequency fl is applied, the phase comparison circuit compares the phase and frequency of the incoming signal with the phase and frequency coming from the VCO. An error voltage is compared which is proportional to the difference between these two frequencies. This error is amplified and filtered by a low frequency signal. This error is fed back to the VCO input and forces the VCO to invert its frequency so that the error signal or difference signal is reduced.

If the input frequency fl is close enough to fo, the VCO will synchronize its operation to the input signal. In other words, the VCO locks to the input frequency. Once this synchronization is accomplished, the VCO frequency becomes nearly identical to the input frequency except for a small phase difference. This small phase difference is necessary, so that a dc output is produced that makes the frequency of VC1 equal to the input frequency.

If the input frequency or phase changes slightly, the dc output will follow this change. Therefore, a PLL can be used as an FM modulator or FM telemetry, and for FSK receivers. FSK maintains frequency shift keying and is a method used to transmit data using frequency modulation of the carrier. A logic level 0 would be a frequency, say 1700 Hz, while a logic level 1 would be represented by a frequency of 1300 Hz. At the transmitter, the logic levels are applied to a VCO to force the output to shift its frequency. The receiver is a PLL that senses the input frequencies and then produces a dc level shift at its output. An FSK receiver using the IC 565 PLL is shown in Figure 6.114. It is intended to receive and decode 1700 Hz and 1300 Hz FSK signals.

Figure 6.114: Basic PLL

The output of the PLL, which is a voltage level dependent on the input frequency, is passed through a three-stage RC filter to remove the carrier frequency. An A710 comparator IC provides a high-level output for the 1300 Hz signal and a low-level output for the 1700 Hz signal. The signaling rate, which is the rate of change between the two strong frequencies, is a maximum of 150 Hz.

Figure 6.115: FSK Receiver/Decoder

1. Important Characteristics of Linear IC Circuits

• Input Bias Current: the average value between two input currents.
• Input offset current: the absolute value of the difference between two input currents at which the output will be controlled higher or lower than a specified voltage.
• Input offset voltage: the absolute value of the voltage between the input terminals required to make the output voltage greater or less than a specified voltage.
• Input voltage region: the voltage region at the input terminals (common mode) where the offset specifications apply.
• Threshold logic voltage: the voltage at the output of a comparator at which loading the logic circuit changes its digital state.
• Negative output level: a negative dc output voltage with the comparator saturated by a differential input that is equal to or greater than the specified voltage.
• Output leakage current: current at the output terminal with an output voltage in a certain region and input control that is equal to or greater than a given value.
• Output resistance: resistance measured across the output terminals with the dc output level at the logic threshold voltage.
• Output dump current: the maximum negative current that the comparator can provide.
• Positive output level: a high output voltage level with a given load and input control that is equal to or greater than a specified value.
• Power consumption: the power required to operate the comparator without any output load. The power will vary with signal level, but is specified as a maximum for the entire range of output signal conditions.
• Response time: the interval between the application of an input step function and the time when the output passes the logic threshold voltage. The input step function controls the comparator from some initial input voltage saturation to an input level required to bring the output from saturation to the logic threshold voltage. This excess is called overdrive.
• Saturation response: a low output voltage level with input control equal to or greater than a specified value.
• Strobe current: the current that comes out of the strobe terminal when the current is at logic zero level.
• Strobe output level: dc output voltage, independent of input conditions, with the voltage at the strobe terminals being equal to or less than a specified low state.
• Strobe ON voltage: the maximum voltage at the strobe terminals required to force the output to the specified high state.
• Strobe OFF pressure: minimum voltage at the strobe terminal that will ensure that this voltage will not interfere with the way the comparator works.
• Strobe time: the time required for the output to rise to the logic threshold voltage after being controlled from zero to logic level one.
• Supply current: the current required from the positive or negative supply to operate the comparator without any output load. The power will vary with input voltage, but this power is specified as a maximum for the entire range of input voltage conditions.
• Voltage gain: the ratio of the change in output voltage to the change in input voltage under stated conditions for the source resistance and load resistance.
• Bandwidth: the frequency at which the voltage gain is reduced to 1/2 of the low frequency value.
• CMRR (Common Mode Rejection Ratio): the ratio of the input common mode voltage region to the peak-to-peak change in the input offset voltage for that region.
• Harmonic distortion: the ratio of harmonic distortion defined as one hundredth of the ratio of the rms (root mean square) of the harmonics to the fundamental.
  
• Input bias current: the average value of the two input currents.
• Input commonmode voltage region: the voltage region at the input terminals in which the amplifier is operated. Note that specifications are not guaranteed in the entire common-mode region, unless specifically stated.
• Input impedance: the ratio of input voltage to input current under stated conditions for source (Rs) and load resistance (RL).
• Input offset current: the difference in currents at the two input terminals when the output is zero.
• Input offset voltage: the voltage that must be applied between the input terminals through two equal resistances to obtain zero output voltage.
• Input resistance: the ratio of the change in input voltage to the change in input current at one input with the other input grounded.
• Input voltage region: the voltage region at the input terminals where the amplifier operates within its specification limits.
• Large signal voltage gain: the ratio of the output voltage swing to the change in input voltage required to drive the output from zero to this voltage.
• Output impedance: the ratio of output voltage to output current under stated conditions for source resistance (Rs) and load resistance (RL).
• Slew rate: the internally limited rate of changes in the output voltage with a large amplitude step function applied to the input.
• Supply current: the current required from the power supply to operate the amplifier under no load conditions and the output is in the middle of the supply.
• Transient response: the closed-loop step function response of an amplifier under small-signal conditions.
• Unity-gain bandwidth: the frequency region from dc to the frequency where the open-loop gain of the amplifier moves toward unity.
• Voltage gain: the ratio of the output voltage to the input voltage under stated conditions for the source resistance (Rs) and load resistance (RL).
• Output resistance: the small signal resistance seen at the output with an output voltage approaching zero.
• Output voltage swing: the peak output voltage swing, referenced to zero, which can be reduced without clipping.
• Offset voltage temperature drift: the average drift rate of the offset voltage for a thermal variation from room temperature to an indicated temperature extreme.
• Power supply rejection: the ratio of the change in the input offset voltage to the change in the power supply voltage that produces it.
• Setting time: the time between the initiation of the input step function and the time when the output voltage has settled within a specified error band of the final output voltage.