Do you know the characteristics/types of digital ICs? In terms of fixing errors in digital circuits, it requires knowledge of the characteristics of the types of components used, and the selection of measurement techniques that can produce the fastest results. In this case, you will be given various abbreviations for logic families along with some explanations regarding their current use.
1. RTL (Resistor Transistor Logic)
This RTL is not made in the form of a monolithic IC. However, discrete circuit blocks are available for industrial purposes that require certain strengths and do not require high speeds (figure 5.2).
Figure 5.2: Example of an RTL circuit
2. DCTL (Direct Coupled Transistor Logic)
This DCTL is the first type that is made like an IC. However, this DCTL had some problems with watching (current hogging) and was soon replaced with a newer type.
3. DTL (Diode Transistor Logic)
This DTL is a commercial IC logic family I available in the market (series 53/73). Now this type is replaced by TTL and CMOS but some factories still produce this DTL (figure 5.3).
Figure 5.3: Example of a DTL circuit
- TTL (Transistor-Transistor Logic)
This type is a very successful logic family with a very wide functional area. The 54/74 series is the standard type (figure 5.4).
Figure 5.4: Example of a TTL circuit
The 54L/74L series for low power The 54H/74H are high speed TTL types. However, the recent development of the Schottky clamp TTL, which prevents these transistors from saturating, has resulted in a significant improvement in performance. These Schottky TTLs are available in the high speed 54S/74S series or the low power 54 LS/74 LS series.
5. ECL (Emitter Coupled Logic)
This ECL is an unsaturated type of transistor logic that works very quickly (10,000 series) figure 5.5.
Figure 5.5: Example of an ECL Circuit
6. CMOS (Complementary Metal Oxide Logic)
This CMOS uses p and n unit MOSFETs and has the advantage of requiring only low power consumption and very good immunity to noise and interference (4000 B series).
7. LOCMOS (Locally Oxidized CMOS)
This type is a type whose performance has been improved if all outputs are buffered. The type numbers are the same as CMOS (figure 5.6).
Figure 5.6: Example of MOS Circuit
8. PMOS (p-Channel MOS)
Widely used for LSI equipment.
9. NMOS (n-Channel MOS)
Used for LSI equipment.
10. I2L (Integrated Injection Logic)
This type is a development of DCTL which allows the use of bipolar technology for LSI equipment (figure 5.7).
Figure 5.7: Example of an IIL circuit
11. SSI (Small Scale Integration)
It is an IC type that has up to 12 equivalent doors per IC package.
12. MSI (Medium Scale Integration)
It is a type of IC that has between 12 and 100 equivalent doors per IC package.
13. LSI (Large Scale Integration)
This type is a type of IC that has an equivalent gate of more than 100 per IC package.
Some of the digital ICs available on the market today are:
- Standard TTL (Type 54 / 74)
- CMOS, LOCMOS (Type 4000 B)
- Low power Schottky TTL (type 54LS / 74LS)
- TTL Schottky (Type 54S / 74 S)
- ECL (Type 10,000) These types will be discussed more in the next section.
Digital ICs must work together in complex circuits, and the problem is the combination of logic levels, the actual voltages that distinguish logic 0 and 1. Table 5-1 shows some characteristics of the four types of logic combinations.
Table 5-1: Characteristics of Some Logic IC Combinations
The TTL family operates on a 5V supply voltage with a 0 level of no more than 0.7 V and a 1 level of no less than 2.15 V. So, this power supply and logic levels are not compatible with ECL (emitter coupled logic) or MOS types. Some types of CMOS are compatible with the TTL family, but not with other ICs.
Table 5-1 shows that CMOS ICs are generally the slowest and ECL ICs are the fastest. In high frequency type counters we will find the high frequency stages, above 150 MHz, implemented in ECL while the low frequency stages are implemented in MOS or CMOS or sometimes TTL logic. The most commonly used digital ICs are the 54-74 family of TTL logic ICs and the 45C-74C family of CMOS ICs.
Each of these two families is characterized by a standard numbering system followed by a general application, which helps to understand the function of that IC part, namely:
- The first two letters indicate the manufacturing code.
- The next two numbers indicate whether the IC is for military or commercial configuration. For example: Number 54 indicates a military version with operating temperature from -55o to +122o Celsius. Number 74 indicates a commercial version with operating temperature from 0-70o Celsius.
- The next one or two letters indicate speed, low power, etc. For example: The letter H indicates a high speed IC, the letter L indicates a low power IC, the letter LS indicates a Schottky process. The letters LS, for example, indicate a low power Schottky device.
- The two or three numbers following it indicate the series of logic section functions.
An example of the identification number on an IC is as follows SN74LS20N. SN indicates the manufacture of Texas Instruments, 74 indicates a commercial IC. LS indicates for low-power Shottky and 20 indicates the IC functions as a 4 input NAND circuit. The last letter N indicates a 14 pin dual inline package (DIP) IC.
For the 54/74 type of the TTL family, there are some very important differences in terms of speed and power dissipation, namely:
- For the standard 54/74 type, it has a delay time of 18 nanoseconds per gate, with a power dissipation of 10 mWatt per gate.
- For the high speed type, it has a delay time of 12 ns and a power dissipation of 23 mWatt.
- For the Low Power type, it has a delay time of 66 ns but the power dissipation is only 1 mWatt.
- For the Schottky type, it has a delay time of 6 ns and a power dissipation of 19 mW, but for low power Schottky (LS) it has a delay time of 19 ns and a power dissipation of only 2mW.
The above characteristics are different from the CMOS 54C / 74C family, where the delay time is 250 ns per gate but the power dissipation is only 0.6 mW. This CMOS family is identical to the legs of the TTL type 54/74 family, only the CMOS power dissipation is much lower. Usually CMOS and MOS ICs use input diode protection circuits, but if the static field is strong enough it will still damage the IC (prevention see Chapter 4.10).
Digital Circuit Failure Tracking
You know that digital ICs are widely used in all branches of electronics, from computing to industrial control, electronic instruments and communication systems (see figure 5.1). In fact, it seems that there is no field in electronics that does not use digital circuits. The main reason for this is that digital circuits work from defined logic levels. In other words, for a signal, if it is high it is usually called logic 1 and if it is low it is called logic 0. This reduces the uncertainty of the output of a circuit. For example, in industrial control, to maintain the safety of a machine when it is closing or opening, it never approaches half-closed or half-open.
Figure 5.1: Examples of Various Digital Equipment
The basic elements of digital circuits are logic gates that perform logical operations on their inputs (See Chapter 11.2.4). Boolean algebra is used to describe these operations. Boolean algebra is based on logical statements that are either true or false, and is thus a very useful tool in designing and troubleshooting digital logic circuits.
Linear IC Circuits and Their Cases
The term linear is used to describe classes of circuits and ICs that respond primarily to analog signals rather than digital signals. Analog signals are variable and can therefore take on any value between some defined limits. A good example of an analog system is the amplification of the small voltage generated by a thermocouple to a level sufficient to give a temperature indication on a 1 mA meter movement. A linear IC, in this case an op-amp, is used as shown in Figure 6.105 to step up the output voltage of the thermocouple. As the temperature measured by the thermocouple varies, a small change in the thermocouple voltage occurs, which is nothing more than an analog signal. The amplifier, operating in its linear region, steps up the thermocouple voltage by a fixed gain factor that depends on the ratio of the feedback resistors. The meter indication can then be calibrated to temperature.
Figure 6.105: Thermocouple Amplifier An Analog Circuit
However, linear ICs do not have to operate in their linear region only, and for example op-amps can be used to produce square wave oscillations and so on as will be discussed in the case section. Many electronics component manufacturers list the following types of circuits under the linear name:
- Op-amp and comparator
- Video amplifier and pulse amplifier
- Audio frequency amplifier and radio frequency amplifier
- Regulators.
- Phase locked loops (PLL)
- Timer
- Multiplier
- Analog to digital converter
- Waveform generator.
So what is related to linear circuits is very broad, therefore it will be considered on some of the more popular types of circuits only. The most widely used IC is the opamp (operational amplifier) with so many different types available on the market.
Finite State Digital Machine Concept
Let us look again at the classical model of a finite state machine (FSM) in Figure 4.1. The delay element can be implemented with a master-slave flip-flop and a clock synchronization signal. Generally, a flip-flop is used for feedback implementation. Note that we can label the flip-flops as we wish, as long as the meaning is clear. In Figure 4.1 the positions of the input Di and the output Qi are interchanged from the normal positions we discussed earlier.
For example, a modulo 4 synchronous counter FSM counts from 00 to 11 and repeats. The block diagram of the synchronous counter FSM is shown in Figure 4.13. The RESET function (positive logic) causes the output values q0 q1 to be 00 when activated. The outputs are sequentially assigned the values on lines q0 and q1 at the times corresponding to the clock. Each time a new output value appears, the feedback value s0s1 also changes.
We note that the design of the counter can be done by listing all possible inputs and outputs that occur on the 4 lines q0 q1 and the state s1 s0. Based on the list, a combinational logic circuit is then created which is the implementation of the counter. Two flip-flops are used to record the state bits.
Figure 4.13 Modulo 4 counter
How do we know that we need 2 bits as state registers for feedback? The reality is that we do not know up front how many bits are needed to register the state, so for the remainder of this section we will look at a more general approach to designing finite state machines. For the counter we can start by constructing a state transition diagram like the one in Figure 4.14 with states A through D and the directed lines indicating the transitions. In this case state A is for the counter value 00, B for 01, C for 10, and D for 11.
Figure 4.14 State transition diagram of a modulo 4 counter
For example, the FSM is initialized in state A. There are 2 possible inputs, namely: 0 and 1. If the input (RESET) is 0, then the FSM will move to state B and produce output 01. If RESET is 1, the FSM remains in state A and produces output 00. Similar to this, if the FSM is in state B, it will move to state C with output 10 if RESET 0, otherwise it will return to state A with output 00. Likewise for other states, can be interpreted in the same way.
Once we have successfully created a state transition diagram, we can write it in the form of a state table as in Figure 4.15. The current state is shown on the left, and the input conditions are at the top. The contents of the table are the next state/output pairs taken directly from the state transition diagram in Figure 4.14. Take one row, for example, the current state is B and the input condition is 0, then the next state is C and the next output is 10.
Figure 4.15 State table for a modulo-4 counter
Once we have created the state table, we assign a binary value to each state. Since there are 4 states, we need at least 2 bits to uniquely encode the state into binary. We simply assign the encodings: A = 00, B = 01, C = 10, and D = 11, and replace each label A, B, C, and D with its state code, as in Figure 4.16. In practice, the assignment of these state codes will affect the shape of the final circuit, but logically these encodings result in the same end result.
Figure 4.16 State table for a modulo-4 counter with its encoding.
From the state table, we can generate truth tables for the next state and output functions as shown in Figure 4.17. The subscripts for the state variables indicate time. The current state is written as st and the next state is written as st+1. Usually these subscripts are omitted in the sense that the right-hand side of the equation contains the current state and the left-hand side contains the next state. Note that s0(t+1) = q0(t+1) and s1(t+1) = q1(t+1), so it is sufficient to implement s0(t + 1) and s1(t + 1) alone while q0(t + 1) and q1(t + 1) can be taken directly from them.
Figure 4.17 Truth table for the next state and output function of a modulo-4 counter.
Finally, we implement the next state and output functions using logic gates and master-slave D flip-flops for the state variables as shown in Figure 4.18.
Digital Sequence Detector Concept
Another example, we will design a machine that outputs a 1 when 2 of the last 3 inputs are 1. For example, the input sequence 011011100 outputs the sequence 001111010. There is one serial input path and we assume that there is initially no input. For this case, we will use a D flip-flop and an 8-to-1 MUX.
Figure 4.18 Logic design for a modulo-4 counter
We begin by constructing a state transition diagram, as in Figure 4.19. There are 8 possible sequences of 3 bits entering the machine: 000, 001, 010, 011, 100, 101, 110, and 111. State A is the initial state, assuming no data has been entered. In states B and C, only 1 bit of data has been entered, so the output is 0. States D, E, F, and G receive at least 2 bits of input if the previous state was B or C. After entering state D, E, F, or G, the system will remain in this state only. State D will be visited when the last two inputs are 00. States E, F, and G will be visited when the last two inputs are 01, 10, and 11.
The next step is to create a state table as shown in Figure 4.20, which is poured from the state transition diagram. Next, we will make a state code assignment as in Figure 4.21a. Based on the state code assignment we can create a truth table for the next state and output function. See Figure 4.21b. The last two rows in the table contain state 111, which in practice will never appear, because state 111 for this case does not exist. Thus the next state and output in the 2 rows do not need to be considered, and are written as 'd' which means don't care, just ignore it.
Finally, we arrange the circuit as shown in Figure 4.22. We need 1 flip-flop for each state variable, so we need 3 flip-flops in total. There are 3 next state functions and 1 output function, so we need 4 MUXs. The selection of s2, s1, and s0 as the MUX controllers is a random choice. Other combinations are also possible.
Figure 4.19 State transition diagram for a sequence detector
Figure 4.20 State table of sequence detector
Digital Sales Machine Controller Concept
We will design a vending machine controller using flip-flops and a 'black box' representing the PLA as shown in Figure 4.23. The vending machine accepts three kinds of coins of Rp 100, Rp 200, and Rp 500. If the value entered is equal to or greater than Rp 400, the machine will dispense the merchandise, return the excess money, and then wait for the next transaction.
We start to construct a state transition diagram like Figure 4.23. In state A, no coins have been inserted, so the money that comes in is Rp 0. If a hundred or two hundred coin is inserted, the state will change to B or C. If a five hundred coin is inserted, the money that comes in is Rp 500. The machine will release the merchandise and give out the change of a hundred coin, and the state remains at A. This is marked with "L/110" in the rotating circle in state A. From state B or C it can move to state D. From D back to A or B.
Figure 4.21 Determining the state code and truth table of the sequence detector
Figure 4.22 Logic diagram of sequence detector
Note when a five hundred coin is inserted in state D. The machine should dispense merchandise, return Rp 400, and return to A, but according to the diagram the machine will dispense merchandise, return Rp 300, and go to state B. The machine still holds Rp 100.
From the state transition diagram, a state table can be constructed as in Figure 4.24a. Then, the state code for the symbols S, D, and L can be determined in binary form, as in Figure 4.24b. Finally, we make the circuit diagram as in Figure 4.25a. The state code consists of 2 bits so that 2 D flip-flops are needed. The four inputs on the PLA are used 2 bits for the current state and 2 bits for coins x1x0. The PLA produces 5 outputs for the next 2 state bits, the item release bit, and the hundredth and two hundredth return bits. We assume that the coin input is considered an input and a beat as well.
The PLA design in Figure 4.25a, can be followed by looking at Figures 4.25b and 4.25c, which are arranged manually. However, for complex cases, computer aids are usually used.
Figure 4.23 State transition diagram of the sales machine controller
Figure 4.24 (a) Sales machine controller state table (b) Sales machine controller state code assignment
Digital System Counter Concept
Counters are another form of register whose outputs have a pattern in a certain range of binary numbers. Figure 4.30 shows the configuration of a modulo 8 counter with the binary pattern for each step being: 000, 001, 010, 011, 100, 101, 110, 111 and repeated. Three JK flip-flops are placed in alternating mode, and each clock input is ANDed with the previous Q output, resulting in a new clock frequency of half. This clock will trigger the next flip-flop, and so on. The result is that each flip-flop Fi will produce an output Qi with a frequency of frac12i. If the Qi pattern with i = 2 to 0 is arranged the result is 000, 001, ... ,111.
Figure 4.30 Modulo 8 counter
In the circuit, an asynchronous RESET line is also added, which will charge the counter to 000, and is independent of the state, the clock line, or the EN line. In addition, the flip-flop on the LSB changes its state due to the state of its neighboring flip-flops, not just because of the clock. This circuit is similar to Figure 4.18 but is easier to expand to a larger size because it only connects the output of the MSB of this unit to the LSB input of the next unit.